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path: root/riscv/decode.h
AgeCommit message (Expand)AuthorFilesLines
2016-05-23When gdb connects, jump to Debug ROM and segfault.Tim Newsome1-1/+6
2016-05-23Gutting direct-access gdb.Tim Newsome1-0/+4
2016-05-23Add writing to DCSR, DPC, DSCRATCH.Tim Newsome1-0/+5
2016-05-21Some bugfixes for CSR reading and setting FS for fflags updates (#43)Andy Wright1-1/+4
2016-03-02Fix ERET serialization strategyAndrew Waterman1-3/+6
2016-03-02Serialize simulator on ERETAndrew Waterman1-0/+6
2016-03-02WIP on priv spec v1.9Andrew Waterman1-3/+2
2016-03-01Upgrade to latest SoftFloatAndrew Waterman1-0/+4
2015-11-12Generate device tree for target machineAndrew Waterman1-0/+1
2015-11-12Access FP regs through a macroAndrew Waterman1-5/+6
2015-10-05more work towards RVC 1.8Andrew Waterman1-4/+3
2015-10-02work towards rvc 1.8Andrew Waterman1-0/+3
2015-09-08Improve instruction fetchAndrew Waterman1-0/+2
2015-09-04Move towards RVC v1.8Andrew Waterman1-22/+19
2015-05-31Add rest of RV32C instructionsAndrew Waterman1-0/+1
2015-05-31New RV64C proposalAndrew Waterman1-24/+35
2015-04-03Support setting ISA/subsets with --isa flagAndrew Waterman1-14/+3
2015-04-02Simplify RV32 comparisonsAndrew Waterman1-1/+0
2015-03-31Allow writing mstatus.fs even if FPU isn't presentAndrew Waterman1-1/+5
2015-03-30Implement RVC draftAndrew Waterman1-6/+38
2015-03-26Serialize counters without throwing C++ exceptionsAndrew Waterman1-0/+4
2015-03-20For misaligned fetch, set mepc = addr of branch/jumpAndrew Waterman1-1/+5
2015-03-12Update to new privileged specAndrew Waterman1-26/+22
2015-02-08Use xlen, not xprlen, to refer to x-register widthAndrew Waterman1-5/+5
2015-01-26Fix commit logAndrew Waterman1-6/+7
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman1-5/+1
2014-12-04Support 2/4/6/8-byte instructionsAndrew Waterman1-19/+21
2014-12-04Set badvaddr on instruction page faultsAndrew Waterman1-1/+1
2014-11-30Implement timer faithfullyAndrew Waterman1-2/+0
2014-09-27Avoid use of __int128_tAndrew Waterman1-5/+1
2014-07-08Disallow access to FCSR when FP is disabledAndrew Waterman1-17/+18
2014-06-13Commit log now prints while interrupts are enabled.Christopher Celio1-6/+2
2014-06-13Only print commit log if instruction commitsAndrew Waterman1-2/+2
2014-01-24Handle CSR permissions correctlyAndrew Waterman1-5/+6
2014-01-13Improve performance for branchy codeAndrew Waterman1-3/+6
2013-12-17Speed things up quite a bitAndrew Waterman1-11/+11
2013-12-09New RDCYCLE encodingAndrew Waterman1-2/+3
2013-11-25Update to new privileged ISAAndrew Waterman1-6/+9
2013-11-05correctly trap when SR_EA is disabledYunsup Lee1-0/+1
2013-09-27Added commit logging (--enable-commitlog). Also fixed disasm bug.Christopher Celio1-0/+27
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman1-22/+4
2013-09-21Update ISA encoding and AUIPC semanticsAndrew Waterman1-11/+15
2013-09-11Implement zany immediatesAndrew Waterman1-91/+30
2013-09-10Add rd field to JAL; drop JAndrew Waterman1-11/+2
2013-08-11Instructions are no longer member functionsAndrew Waterman1-17/+18
2013-08-08Disentangle some header filesAndrew Waterman1-0/+1
2013-07-26Remove more vector stuffAndrew Waterman1-60/+3
2013-07-26Rip out RVC for nowAndrew Waterman1-27/+11
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-1/+1
2013-04-24fixes to correctly simulate the vector unitYunsup Lee1-0/+2
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