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path: root/riscv/decode.h
AgeCommit message (Expand)AuthorFilesLines
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-1/+2
2013-03-25support compilation with gcc 4.7Andrew Waterman1-0/+1
2013-01-25change htif to link against libfesvrAndrew Waterman1-3/+14
2012-03-24new supervisor modeAndrew Waterman1-15/+1
2012-03-19abstract regfile write portAndrew Waterman1-14/+30
2012-03-19abstract regfile behind objectAndrew Waterman1-20/+20
2012-01-22disentangle decode.h from other headersAndrew Waterman1-16/+0
2012-01-22work around gcc 4.4 bugAndrew Waterman1-2/+2
2011-11-11Changed supervisor modeAndrew Waterman1-5/+0
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+301
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-301/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-10/+9
2011-06-11[xcc] instructions now set PC explicitlyAndrew Waterman1-0/+14
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-7/+6
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-0/+1
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee1-5/+12
2011-05-13[sim] initial support for virtual memoryAndrew Waterman1-1/+2
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman1-3/+9
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman1-4/+7
2011-04-16[sim] removed undefined behavior for non-canonical inputsAndrew Waterman1-1/+3
2011-04-12[xcc,sim] fixed RM fieldAndrew Waterman1-2/+4
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman1-1/+7
2011-04-11[sim] fixed FSR exception field bugAndrew Waterman1-1/+1
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-0/+6
2011-04-09[sim] add vt stuffYunsup Lee1-0/+45
2011-04-09[sim,pk] reorganized status registerAndrew Waterman1-9/+9
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-8/+15
2011-03-01[xcc,sim] branches are pc-relative (not pc+4) againAndrew Waterman1-2/+2
2011-02-04[sim,pk] added interrupt-pending field to cause regAndrew Waterman1-0/+5
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman1-0/+1
2011-02-01[sim] added nearest/ties to max magnitude rounding modeAndrew Waterman1-3/+7
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-3/+2
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-34/+23
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-23/+23
2010-12-27[sim] cleaned up handling of link registerAndrew Waterman1-0/+1
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-1/+2
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-16/+27
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman1-5/+4
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman1-0/+1
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman1-1/+16
2010-10-11[sim] added writeback tracingAndrew Waterman1-2/+26
2010-10-05[xcc] removed CEXC field from FSRAndrew Waterman1-15/+5
2010-09-23[xcc, sim] eliminated zero-extended immediatesAndrew Waterman1-3/+2
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-22/+24
2010-09-12[xcc, sim] moved shamt field and renamed shiftsAndrew Waterman1-3/+4
2010-09-12[xcc, sim] branches now are next-PC-based, not PC-basedAndrew Waterman1-2/+2
2010-09-10[sim, pk] cleaned up exception vectors and FP exc flagsAndrew Waterman1-3/+12
2010-09-09[pk, sim] added interrupt support to sim; added timer interruptAndrew Waterman1-2/+4
2010-09-07[sim, xcc] branches now have 2-byte-aligned displacementsAndrew Waterman1-2/+4
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