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AgeCommit message (Expand)AuthorFilesLines
2019-11-12Remove S-mode CSRs when S-mode is not presentAndrew Waterman1-1/+2
2019-11-11rvv: add 'V' ext check for each vector insnChih-Min Chao1-1/+1
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao1-5/+0
2019-11-11rvv: add reg checking rule for ldstChih-Min Chao1-3/+12
2019-11-11rvv: add reg checking rule for general fomratChih-Min Chao1-1/+21
2019-11-11rvv: add reg checking rule for comparison instrucitonsChih-Min Chao1-1/+19
2019-11-11rvv: add reg checking rule for reductionChih-Min Chao1-5/+12
2019-11-11rvv: add register using check for wide and narrow insnChih-Min Chao1-33/+48
2019-11-11rvv: fix INT_ROUNDING complianceAlbert Ou1-14/+10
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao1-100/+7
2019-11-11rvv: fix redsum/vmv for non-tail-zero caseChih-Min Chao1-5/+7
2019-10-29rvv: fix floating-point exception for comparisonChih-Min Chao1-0/+1
2019-10-28Implement support for big-endian hostsMarcus Comstedt1-16/+23
2019-10-22Stop loading "past the end" of the vector. (#351)Nick Knight1-5/+5
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman1-7/+14
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-0/+3
2019-07-05Avoid static initializers for variable-length arraysAndrew Waterman1-2/+2
2019-06-18rvv: add floating-point instructionsChih-Min Chao1-1/+264
2019-06-18rvv: add load/store instructionsChih-Min Chao1-0/+151
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao1-0/+1041
2019-06-18rvv: add control instructions and system register accessChih-Min Chao1-0/+1
2019-06-14rvv: disasm: add v-spec 0.7.1 supportChih-Min Chao1-0/+10
2019-04-02Implement debug hasel support (#287)Tim Newsome1-0/+3
2018-08-23Fix several disassembler bugsAndrew Waterman1-0/+1
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman1-0/+6
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman1-1/+1
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman1-3/+3
2017-10-20Fix commit-log for Q extension, and for RV32 (#143)Andrew Waterman1-2/+2
2017-09-28Implement Q extensionAndrew Waterman1-11/+32
2017-04-19Fix builds with "--enable-commitlog"Palmer Dabbelt1-1/+1
2017-04-18debug: Use Debug-Module specific constants instead of global defines.Megan Wachs1-13/+0
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some b...Megan Wachs1-8/+5
2017-04-17debug: Move things around, but addresses now conflict with ROM.Megan Wachs1-8/+13
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs1-10/+31
2017-04-10Implement new FP encodingAndrew Waterman1-5/+21
2017-03-27Set badaddr=0 on illegal instruction trapsAndrew Waterman1-3/+3
2017-03-23Require little-endian hostAndrew Waterman1-0/+4
2017-02-20serialize simulator on wfiAndrew Waterman1-2/+3
2017-02-13Abstract register read mostly working.Tim Newsome1-3/+9
2017-02-10Entering debug mode now jumps to "dynamic rom"Tim Newsome1-10/+6
2016-06-01Move sethaltnot and cleardebint.Tim Newsome1-2/+2
2016-05-24Move cleardebint, per spec.Tim Newsome1-1/+1
2016-05-23Remove dependency on include file in my homedir.Tim Newsome1-5/+0
2016-05-23Software breakpoints sort of work.Tim Newsome1-6/+0
2016-05-23Exceptions in Debug Mode, stay in Debug Mode.Tim Newsome1-0/+1
2016-05-23Have Debug memory kind of working again.Tim Newsome1-6/+6
2016-05-23Add debug_module bus device.Tim Newsome1-3/+6
2016-05-23Make sure to translate Debug RAM addresses also.Tim Newsome1-0/+3
2016-05-23Clean up how Debug ROM is included.Tim Newsome1-1/+1
2016-05-23Can jump to and execute Debug ROM.Tim Newsome1-2/+5
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