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2020-05-27rvv: index register doesn't care about NFsifive/rvv0.9-phase2Chih-Min Chao1-3/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-27rvv: fix ext alignment checking for src and dstChih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-27rvv: v[z|s]ext: remove redundant requiresDave.Wen1-2/+0
2020-05-25rvv: add e8 type for scaleChih-Min Chao1-3/+17
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-25rvv: fix wrong vill checkingChih-Min Chao1-1/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-24rvv: support [u]i8 typeChih-Min Chao1-3/+8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: dont't handle slen != vlenChih-Min Chao1-8/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: remove duplicated CI_BI macroChih-Min Chao1-10/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: refine comparision checkingChih-Min Chao1-8/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: remove vmlenChih-Min Chao1-9/+7
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: refine vl length and elemnet size checkingChih-Min Chao1-4/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: update the exception rules for v[m]adc/v[m]sbcDave.Wen1-4/+12
2020-05-21rvv: fix index load/store emul/nf checkingChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: src can't overlap dst for extChih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: fix index checkingChih-Min Chao1-1/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: v[z|s]extDave.Wen1-40/+6
2020-05-21rvv: index should align vemulChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-21rvv: fix atomicChih-Min Chao1-3/+9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20wip: v[z|s]extDave.Wen1-6/+47
2020-05-20rvv: fix index load/storeChih-Min Chao1-26/+24
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: refine st_indexChih-Min Chao1-8/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: refine ld_indexChih-Min Chao1-7/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: make overlap handling zero sizeChih-Min Chao1-4/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: remove debugChih-Min Chao1-1/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: fix out of range checking unit/stridedChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: wrap vm checkingChih-Min Chao1-14/+8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-20rvv: refine overlapd and align checkingChih-Min Chao1-38/+43
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19rvv: fix widen checkingChih-Min Chao1-4/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-19rvv: store eew and emul to P.VU for unit/stride load/storeChih-Min Chao1-22/+21
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix unit/stride emul calculationChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix compiler warningChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: fix unit/strided load/store checking ruleChih-Min Chao1-29/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-18rvv: MLEN=1 overlappingDave.Wen1-4/+4
2020-05-17rvv: mlen=1 WIPDave.Wen1-3/+4
2020-05-14rvv: amo: only allow 32/64 bit elementChih-Min Chao1-14/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: add vzext/vsextChih-Min Chao1-0/+32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: dont't explicit throw exceptionChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-14rvv: fix the fractional lmulDave.Wen1-1/+1
2020-05-13rvv: wrong operation to the fractional LMUL bitDave.Wen1-1/+1
2020-05-13rvv: change to 0.9amoChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: amo pre-0.9Chih-Min Chao1-0/+52
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen1-4/+4
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen1-0/+3
2020-05-13eew: add eewDave.Wen1-8/+17
2020-05-13eew: fix the eew=0 caseDave.Wen1-13/+16
2020-05-12rvv: ldst: add missng check for VI_LDChih-Min Chao1-2/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-11rvv: change to 0.9 ldstChih-Min Chao1-69/+83
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen1-2/+23
2020-04-27rvv: align VCSR with upstreamChih-Min Chao1-4/+4
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-27rvv: commitlog: fix comparision dst informationChih-Min Chao1-4/+7
Comparison only writes one vector register Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-07-11 06:21:40 +0000