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path: root/riscv/decode.h
AgeCommit message (Expand)AuthorFilesLines
2020-04-24rvv: commitlog: fix dst information for int comparisonChih-Min Chao1-20/+40
2020-04-23rvv: aad fp16 support for vfwxxx.[wv]vChih-Min Chao1-8/+20
2020-04-22rvv: fix segment load/store nf checkingChih-Min Chao1-5/+7
2020-04-21rvv: fix floating comparison for fp16Chih-Min Chao1-11/+22
2020-04-21rvv: allow fp16Chih-Min Chao1-1/+2
2020-04-15rvv: add narrow conversion instrucitonsChih-Min Chao1-0/+27
2020-04-15rvv: add normal and widen reduction instructionsChih-Min Chao1-15/+42
2020-04-15rvv: add vmfxx f16 compare instructionsChih-Min Chao1-2/+9
2020-04-15rvv: add .vf fp16 instructionsChih-Min Chao1-3/+9
2020-04-15rvv: add .vv fp16 instructionsChih-Min Chao1-2/+9
2020-04-15rvv: WIDE_END loop macroChih-Min Chao1-9/+4
2020-04-15fp16: add helper macroChih-Min Chao1-0/+8
2020-04-14rvv: leave only SEW-bit segment storeChih-Min Chao1-2/+2
2020-04-14rvv: leave only sew-wise segment loadChih-Min Chao1-8/+12
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+9
2020-04-14rvv: add new vcsr vector csrChih-Min Chao1-4/+4
2020-04-10rvv: remove unecessary initializationChih-Min Chao1-1/+0
2020-04-10rvv: fix index segment load overlapping checkChih-Min Chao1-5/+7
2020-04-10rvv: missing vector enabling check for mask operationChih-Min Chao1-0/+1
2020-03-23rvv: restrict segment load register ruleChih-Min Chao1-3/+1
2020-03-11commitlog: fix missing dump for some instructionsChih-Min Chao1-4/+4
2020-03-05rvv: update the vector fredsum algorithmZhen Wei1-15/+23
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei1-0/+53
2020-03-03commitlog: fix conditional building errorChih-Min Chao1-1/+3
2020-03-03commitlog: enhance vector dumpChih-Min Chao1-0/+1
2020-03-03Debug can actually start at 0x0 nowAndrew Waterman1-2/+1
2020-03-03rvv: vstart must be 0 for reduction instructionsChih-Min Chao1-0/+1
2020-03-04rvv: remove the option of vector misaligned accessZhen Wei1-4/+2
2020-03-04rvv: remove the option of vector impl. checkZhen Wei1-19/+0
2020-02-20Revert "rvv modify the vfredsum.vs behavior with e27 xlen=32"Max Lin1-0/+1
2020-02-20rvv modify the vfredsum.vs behavior with e27 xlen=32Max Lin1-1/+0
2020-02-20rvv: only check segment overlapping in index loadChih-Min Chao1-4/+2
2020-02-19rvv: don't zero vstart in the beginningChih-Min Chao1-1/+0
2020-02-19Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman1-9/+16
2020-02-19widening reductions are legal when LMUL=8Andrew Waterman1-1/+0
2020-02-19vadc/vsbc: allow v0 overlap if LMUL = 1Andrew Waterman1-2/+2
2020-02-14rvv: make variable name match its meaningChih-Min Chao1-1/+1
2020-02-14rvv: fix exception rethrow in fault-first loadChih-Min Chao1-1/+1
2020-02-12rvv: respect vstart in fault-first loadChih-Min Chao1-3/+3
2020-02-12commitlog: rvv: add commitlog support to integer instructionsChih-Min Chao1-33/+33
2020-02-12commitlog: rvv: add commitlog support to float instrunctionsChih-Min Chao1-11/+11
2020-02-12commitlog: rvv: add commitlog support to load instructionsChih-Min Chao1-8/+9
2020-02-12commitlog: rvv: change vector register read/write interfaceChih-Min Chao1-0/+4
2020-02-12commitlog: extend reg record to keep multiple accesssChih-Min Chao1-2/+2
2020-02-12state: rewrite state_t initializationChih-Min Chao1-0/+8
2020-01-13rvv: segment load/store needs to check destination rangeChih-Min Chao1-2/+3
2019-12-19rvv: Detect too-long segment before starting a vector loadAndrew Waterman1-4/+2
2019-12-19rvv: fix the exception behavior for fault-first loadAndrew Waterman1-11/+14
2019-12-12rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao1-3/+1
2019-12-12rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 supportChih-Min Chao1-12/+28
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