aboutsummaryrefslogtreecommitdiff
path: root/riscv/decode.h
AgeCommit message (Expand)AuthorFilesLines
2020-05-19rvv: fix widen checkingChih-Min Chao1-4/+10
2020-05-19rvv: store eew and emul to P.VU for unit/stride load/storeChih-Min Chao1-22/+21
2020-05-18rvv: fix unit/stride emul calculationChih-Min Chao1-3/+3
2020-05-18rvv: fix compiler warningChih-Min Chao1-1/+1
2020-05-18rvv: fix unit/strided load/store checking ruleChih-Min Chao1-29/+18
2020-05-18rvv: MLEN=1 overlappingDave.Wen1-4/+4
2020-05-17rvv: mlen=1 WIPDave.Wen1-3/+4
2020-05-14rvv: amo: only allow 32/64 bit elementChih-Min Chao1-14/+1
2020-05-14rvv: add vzext/vsextChih-Min Chao1-0/+32
2020-05-14rvv: dont't explicit throw exceptionChih-Min Chao1-1/+1
2020-05-14rvv: fix the fractional lmulDave.Wen1-1/+1
2020-05-13rvv: wrong operation to the fractional LMUL bitDave.Wen1-1/+1
2020-05-13rvv: change to 0.9amoChih-Min Chao1-2/+2
2020-05-13rvv: amo pre-0.9Chih-Min Chao1-0/+52
2020-05-13rvv: fractional_lmul when lmul < 1Dave.Wen1-4/+4
2020-05-13vtype: fix the vta and vma functions and debugging displayDave.Wen1-0/+3
2020-05-13eew: add eewDave.Wen1-8/+17
2020-05-13eew: fix the eew=0 caseDave.Wen1-13/+16
2020-05-12rvv: ldst: add missng check for VI_LDChih-Min Chao1-2/+1
2020-05-11rvv: change to 0.9 ldstChih-Min Chao1-69/+83
2020-05-07rvv: add eew and lmul for vle/vse/vleffDave.Wen1-2/+23
2020-04-27rvv: align VCSR with upstreamChih-Min Chao1-4/+4
2020-04-27rvv: commitlog: fix comparision dst informationChih-Min Chao1-4/+7
2020-04-24rvv: commitlog: fix dst information for int comparisonChih-Min Chao1-20/+40
2020-04-23rvv: aad fp16 support for vfwxxx.[wv]vChih-Min Chao1-8/+20
2020-04-22rvv: fix segment load/store nf checkingChih-Min Chao1-5/+7
2020-04-21rvv: fix floating comparison for fp16Chih-Min Chao1-11/+22
2020-04-21rvv: allow fp16Chih-Min Chao1-1/+2
2020-04-15rvv: add narrow conversion instrucitonsChih-Min Chao1-0/+27
2020-04-15rvv: add normal and widen reduction instructionsChih-Min Chao1-15/+42
2020-04-15rvv: add vmfxx f16 compare instructionsChih-Min Chao1-2/+9
2020-04-15rvv: add .vf fp16 instructionsChih-Min Chao1-3/+9
2020-04-15rvv: add .vv fp16 instructionsChih-Min Chao1-2/+9
2020-04-15rvv: WIDE_END loop macroChih-Min Chao1-9/+4
2020-04-15fp16: add helper macroChih-Min Chao1-0/+8
2020-04-14rvv: leave only SEW-bit segment storeChih-Min Chao1-2/+2
2020-04-14rvv: leave only sew-wise segment loadChih-Min Chao1-8/+12
2020-04-14rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao1-0/+9
2020-04-14rvv: add new vcsr vector csrChih-Min Chao1-4/+4
2020-04-10rvv: remove unecessary initializationChih-Min Chao1-1/+0
2020-04-10rvv: fix index segment load overlapping checkChih-Min Chao1-5/+7
2020-04-10rvv: missing vector enabling check for mask operationChih-Min Chao1-0/+1
2020-03-23rvv: restrict segment load register ruleChih-Min Chao1-3/+1
2020-03-11commitlog: fix missing dump for some instructionsChih-Min Chao1-4/+4
2020-03-05rvv: update the vector fredsum algorithmZhen Wei1-15/+23
2020-03-05rvv: import parallel vf(w)redsum hardware impl.Zhen Wei1-0/+53
2020-03-03commitlog: fix conditional building errorChih-Min Chao1-1/+3
2020-03-03commitlog: enhance vector dumpChih-Min Chao1-0/+1
2020-03-03Debug can actually start at 0x0 nowAndrew Waterman1-2/+1
2020-03-03rvv: vstart must be 0 for reduction instructionsChih-Min Chao1-0/+1
generated by cgit v1.1 at 2024-07-11 10:18:52 +0000