index
:
rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
riscv
/
decode.h
Age
Commit message (
Expand
)
Author
Files
Lines
2020-05-27
rvv: index register doesn't care about NF
sifive/rvv0.9-phase2
Chih-Min Chao
1
-3
/
+1
2020-05-27
rvv: fix ext alignment checking for src and dst
Chih-Min Chao
1
-0
/
+2
2020-05-27
rvv: v[z|s]ext: remove redundant requires
Dave.Wen
1
-2
/
+0
2020-05-25
rvv: add e8 type for scale
Chih-Min Chao
1
-3
/
+17
2020-05-25
rvv: fix wrong vill checking
Chih-Min Chao
1
-1
/
+3
2020-05-24
rvv: support [u]i8 type
Chih-Min Chao
1
-3
/
+8
2020-05-21
rvv: dont't handle slen != vlen
Chih-Min Chao
1
-8
/
+1
2020-05-21
rvv: remove duplicated CI_BI macro
Chih-Min Chao
1
-10
/
+2
2020-05-21
rvv: refine comparision checking
Chih-Min Chao
1
-8
/
+6
2020-05-21
rvv: remove vmlen
Chih-Min Chao
1
-9
/
+7
2020-05-21
rvv: refine vl length and elemnet size checking
Chih-Min Chao
1
-4
/
+4
2020-05-21
rvv: update the exception rules for v[m]adc/v[m]sbc
Dave.Wen
1
-4
/
+12
2020-05-21
rvv: fix index load/store emul/nf checking
Chih-Min Chao
1
-0
/
+1
2020-05-21
rvv: src can't overlap dst for ext
Chih-Min Chao
1
-0
/
+1
2020-05-21
rvv: fix index checking
Chih-Min Chao
1
-1
/
+5
2020-05-21
rvv: v[z|s]ext
Dave.Wen
1
-40
/
+6
2020-05-21
rvv: index should align vemul
Chih-Min Chao
1
-1
/
+1
2020-05-21
rvv: fix atomic
Chih-Min Chao
1
-3
/
+9
2020-05-20
wip: v[z|s]ext
Dave.Wen
1
-6
/
+47
2020-05-20
rvv: fix index load/store
Chih-Min Chao
1
-26
/
+24
2020-05-20
rvv: refine st_index
Chih-Min Chao
1
-8
/
+10
2020-05-20
rvv: refine ld_index
Chih-Min Chao
1
-7
/
+10
2020-05-20
rvv: make overlap handling zero size
Chih-Min Chao
1
-4
/
+5
2020-05-20
rvv: remove debug
Chih-Min Chao
1
-1
/
+0
2020-05-20
rvv: fix out of range checking unit/strided
Chih-Min Chao
1
-3
/
+3
2020-05-20
rvv: wrap vm checking
Chih-Min Chao
1
-14
/
+8
2020-05-20
rvv: refine overlapd and align checking
Chih-Min Chao
1
-38
/
+43
2020-05-19
rvv: fix widen checking
Chih-Min Chao
1
-4
/
+10
2020-05-19
rvv: store eew and emul to P.VU for unit/stride load/store
Chih-Min Chao
1
-22
/
+21
2020-05-18
rvv: fix unit/stride emul calculation
Chih-Min Chao
1
-3
/
+3
2020-05-18
rvv: fix compiler warning
Chih-Min Chao
1
-1
/
+1
2020-05-18
rvv: fix unit/strided load/store checking rule
Chih-Min Chao
1
-29
/
+18
2020-05-18
rvv: MLEN=1 overlapping
Dave.Wen
1
-4
/
+4
2020-05-17
rvv: mlen=1 WIP
Dave.Wen
1
-3
/
+4
2020-05-14
rvv: amo: only allow 32/64 bit element
Chih-Min Chao
1
-14
/
+1
2020-05-14
rvv: add vzext/vsext
Chih-Min Chao
1
-0
/
+32
2020-05-14
rvv: dont't explicit throw exception
Chih-Min Chao
1
-1
/
+1
2020-05-14
rvv: fix the fractional lmul
Dave.Wen
1
-1
/
+1
2020-05-13
rvv: wrong operation to the fractional LMUL bit
Dave.Wen
1
-1
/
+1
2020-05-13
rvv: change to 0.9amo
Chih-Min Chao
1
-2
/
+2
2020-05-13
rvv: amo pre-0.9
Chih-Min Chao
1
-0
/
+52
2020-05-13
rvv: fractional_lmul when lmul < 1
Dave.Wen
1
-4
/
+4
2020-05-13
vtype: fix the vta and vma functions and debugging display
Dave.Wen
1
-0
/
+3
2020-05-13
eew: add eew
Dave.Wen
1
-8
/
+17
2020-05-13
eew: fix the eew=0 case
Dave.Wen
1
-13
/
+16
2020-05-12
rvv: ldst: add missng check for VI_LD
Chih-Min Chao
1
-2
/
+1
2020-05-11
rvv: change to 0.9 ldst
Chih-Min Chao
1
-69
/
+83
2020-05-07
rvv: add eew and lmul for vle/vse/vleff
Dave.Wen
1
-2
/
+23
2020-04-27
rvv: align VCSR with upstream
Chih-Min Chao
1
-4
/
+4
2020-04-27
rvv: commitlog: fix comparision dst information
Chih-Min Chao
1
-4
/
+7
[next]