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path: root/riscv/decode.h
AgeCommit message (Expand)AuthorFilesLines
2021-09-08Move enable detections into sstatus_csr_tScott Johnson1-3/+3
2021-09-08Move dirtying logic into sstatus_csr_tScott Johnson1-3/+3
2021-09-08Rename supports_extension() to extension_enabled()Scott Johnson1-10/+10
2021-09-08Convert mstatus into csr_t familyScott Johnson1-3/+3
2021-09-08Remove no-longer-necessary explicit setting of *status.SD bitScott Johnson1-3/+3
2021-09-08Convert vsstatus to csr_t familyScott Johnson1-3/+3
2021-09-08Extract function for dirty_mstatus()Scott Johnson1-7/+3
2021-07-26Fix several bugs in P-extension register-pair handlingAndrew Waterman1-9/+7
2021-07-26decode: op: remove quad related macro and defineChih-Min Chao1-79/+0
2021-06-02Fix ambiguous if/else warningAndrew Waterman1-1/+1
2021-06-02Fix CSR read-only check regression introduced in 463001198Andrew Waterman1-1/+5
2021-05-10Support RISC-V p-ext-proposal v0.9.2 (#637)ChunPing Chung1-0/+509
2021-05-01Improve coding style of logging printfsAndrew Waterman1-1/+2
2021-03-05Fix vsstatus.FS misbehavior (#661)Scott Johnson1-7/+10
2021-02-24rvv: add vsetivliChih-Min Chao1-0/+1
2021-02-24rvv: add vse1/vle1Chih-Min Chao1-12/+12
2021-02-17Fix require_vector_vs() for H-extensionAnup Patel1-1/+1
2021-02-16fix require fp since spec said <When V=1, both vsstatus.FS and the HS… (#646)francis40961-1/+1
2021-01-22scalar-crypto: Initial spike support for v0.8.1 (#635)Ben Marshall1-0/+3
2020-12-14rvv: fix the v[z|s]ext about elmul checking.Dave.Wen1-1/+1
2020-12-14disasm: show fench's predecessor and successorChih-Min Chao1-0/+1
2020-12-04rvv: check the vz/sext's eewDave.Wen1-0/+1
2020-11-11mmu: add impl table and set functionChih-Min Chao1-0/+1
2020-10-26rvv: check extra dst for index segment loadChih-Min Chao1-12/+15
2020-10-06rvv: vamo needs to keep exception index in vstartChih-Min Chao1-0/+1
2020-10-01decode: only return meaningful bits for insn_t (#561)Chih-Min Chao1-1/+1
2020-09-22rvv: fix vfncvt/vfwcvt type checkingChih-Min Chao1-1/+6
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman1-13/+1
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman1-6/+6
2020-08-31rvv: relax checking for vs1Chih-Min Chao1-0/+29
2020-08-31rvv: trigger exp for illegal ncvt/wcvt eewChih-Min Chao1-1/+2
2020-08-31rvv: check invalid frm for floating operationsChih-Min Chao1-0/+2
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao1-16/+20
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao1-5/+0
2020-07-29rvv: remove veew/vemul stateChih-Min Chao1-27/+25
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao1-0/+60
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman1-2/+2
2020-07-09Implement hypervisor CSRs read/writeAnup Patel1-3/+12
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao1-3/+5
2020-06-25rvv: remove unecessary accessChih-Min Chao1-3/+0
2020-06-15remove the redundant code (#488)Dave Wen1-1/+0
2020-06-11rvv: fix index and amo overlapping ruleChih-Min Chao1-4/+23
2020-06-11rvv: add widen overlapping helper and related widen ruleChih-Min Chao1-8/+52
2020-06-11rvv: fix comparison and narrow overlapping ruleChih-Min Chao1-3/+6
2020-06-04rvv: fix compilation warningChih-Min Chao1-6/+6
2020-05-28rvv: use zvqmac to enable vector qmacChih-Min Chao1-0/+1
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao1-53/+46
2020-05-28rvv: add e8 type for narrow/widen conversionChih-Min Chao1-5/+24
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