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path: root/riscv/decode.h
AgeCommit message (Expand)AuthorFilesLines
2015-03-12Update to new privileged specAndrew Waterman1-26/+22
2015-02-08Use xlen, not xprlen, to refer to x-register widthAndrew Waterman1-5/+5
2015-01-26Fix commit logAndrew Waterman1-6/+7
2015-01-02On misaligned fetch, set EPC to target, not branch itselfAndrew Waterman1-5/+1
2014-12-04Support 2/4/6/8-byte instructionsAndrew Waterman1-19/+21
2014-12-04Set badvaddr on instruction page faultsAndrew Waterman1-1/+1
2014-11-30Implement timer faithfullyAndrew Waterman1-2/+0
2014-09-27Avoid use of __int128_tAndrew Waterman1-5/+1
2014-07-08Disallow access to FCSR when FP is disabledAndrew Waterman1-17/+18
2014-06-13Commit log now prints while interrupts are enabled.Christopher Celio1-6/+2
2014-06-13Only print commit log if instruction commitsAndrew Waterman1-2/+2
2014-01-24Handle CSR permissions correctlyAndrew Waterman1-5/+6
2014-01-13Improve performance for branchy codeAndrew Waterman1-3/+6
2013-12-17Speed things up quite a bitAndrew Waterman1-11/+11
2013-12-09New RDCYCLE encodingAndrew Waterman1-2/+3
2013-11-25Update to new privileged ISAAndrew Waterman1-6/+9
2013-11-05correctly trap when SR_EA is disabledYunsup Lee1-0/+1
2013-09-27Added commit logging (--enable-commitlog). Also fixed disasm bug.Christopher Celio1-0/+27
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman1-22/+4
2013-09-21Update ISA encoding and AUIPC semanticsAndrew Waterman1-11/+15
2013-09-11Implement zany immediatesAndrew Waterman1-91/+30
2013-09-10Add rd field to JAL; drop JAndrew Waterman1-11/+2
2013-08-11Instructions are no longer member functionsAndrew Waterman1-17/+18
2013-08-08Disentangle some header filesAndrew Waterman1-0/+1
2013-07-26Remove more vector stuffAndrew Waterman1-60/+3
2013-07-26Rip out RVC for nowAndrew Waterman1-27/+11
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-1/+1
2013-04-24fixes to correctly simulate the vector unitYunsup Lee1-0/+2
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-1/+2
2013-03-25support compilation with gcc 4.7Andrew Waterman1-0/+1
2013-01-25change htif to link against libfesvrAndrew Waterman1-3/+14
2012-03-24new supervisor modeAndrew Waterman1-15/+1
2012-03-19abstract regfile write portAndrew Waterman1-14/+30
2012-03-19abstract regfile behind objectAndrew Waterman1-20/+20
2012-01-22disentangle decode.h from other headersAndrew Waterman1-16/+0
2012-01-22work around gcc 4.4 bugAndrew Waterman1-2/+2
2011-11-11Changed supervisor modeAndrew Waterman1-5/+0
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+301
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-301/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-10/+9
2011-06-11[xcc] instructions now set PC explicitlyAndrew Waterman1-0/+14
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-7/+6
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-0/+1
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee1-5/+12
2011-05-13[sim] initial support for virtual memoryAndrew Waterman1-1/+2
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman1-3/+9
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman1-4/+7
2011-04-16[sim] removed undefined behavior for non-canonical inputsAndrew Waterman1-1/+3
2011-04-12[xcc,sim] fixed RM fieldAndrew Waterman1-2/+4
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