aboutsummaryrefslogtreecommitdiff
path: root/riscv/debug_module.h
AgeCommit message (Collapse)AuthorFilesLines
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-1/+1
* Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state.
2019-05-14Clean up debug module options. (#299)Tim Newsome1-12/+14
* Clean up debug module options. 1. Instead of passing each one a few levels deep, create debug_module_config_t which contains them all. 2. Rename all those command line options so they start with --dm for debug module. 3. Add --dm-no-halt-groups to disable halt group support. * Update changelog.
2019-04-04Add --debug-no-abstract-csr (#267)Tim Newsome1-1/+3
This is used to make sure that OpenOCD can work on targets that don't support abstract access to CSR registers. It replaces a simpler hack, which caused #266.
2019-04-02Implement debug hasel support (#287)Tim Newsome1-2/+7
* Implement hasel/hawindow support. This should allow simultaneous resume and halt to work. * Fix anyrunning/anyhalted bits. * Add --without-hasel argument for testing. * Make halt/resume times more equal. Switching threads after every instruction executed in debug mode leads to a lot of extra instructions being executed on the "other" thread when both are really supposed to halt/resume near-simultaneously. Fixed that by adding wfi to debug_rom.S, and implementing it to switch to the other hart as well as check for JTAG input. When resuming, write the hart ID to the debug ROM so that the DM knows which hart actually resumed. (Before simultaneous resume it just assumed the current one.) Also got rid of resume symbol in debug_rom.S since it had no purpose. * Preserve Debug ROM entry points. * Make sure minstret is correct when wfi happens.
2019-03-04Implement halt groups (#280)Tim Newsome1-4/+10
* Update debug_defines from latest spec. * Implement halt groups. This lets the debugger halt multiple harts near simultaneously. * Revert encoding, which I updated accidentally.
2018-12-13Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome1-2/+13
Optionally make spike behave more like real hardware, to automatically test OpenOCD's handling of such hardware.
2018-08-23Add dummy custom debug registers, to test OpenOCD. (#233)Tim Newsome1-0/+3
2018-06-11Update debug_defines.hTim Newsome1-0/+2
Add support for hartselhi parsing, but other parts of the debug code still don't support more than 1024 harts.
2018-03-16Implement debug havereset bitsTim Newsome1-1/+7
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome1-2/+13
Add debug module authentication.
2018-02-27Add debug module authentication.Tim Newsome1-2/+13
Off by default, enabled with --debug-auth. The protocol is very simple (definitely not secure) to allow debuggers to test their authentication feature. To authenticate a debugger must: 1. Read authdata 2. Write to authdata the value that it just read, plus 1
2018-02-19WIP. Doesn't work.Tim Newsome1-1/+1
2018-02-01Add --debug-sba optionTim Newsome1-1/+2
This lets the user control whether the system bus access implements bus mastering.
2018-01-29Update debug_definesTim Newsome1-0/+2
2018-01-18Support debug system bus access.Tim Newsome1-0/+24
2017-12-11Set impebreak.Tim Newsome1-0/+1
2017-12-11Update to latest debug_defines.h.Tim Newsome1-5/+4
2017-12-11Make progbuf a run-time option.Tim Newsome1-6/+12
Also add an implicit ebreak after the program buffer. This is not part of the spec, but hopefully it will be.
2017-04-18debug: Use Debug-Module specific constants instead of global defines.Megan Wachs1-4/+10
2017-04-18debug: Checkpoint which somewhat works with OpenOCD v13, but still has some ↵Megan Wachs1-8/+3
bugs.
2017-04-17debug: Move things around, but addresses now conflict with ROM.Megan Wachs1-22/+15
2017-03-21spec bumpPalmer Dabbelt1-19/+26
2017-02-25Update bits to latest spec.Tim Newsome1-7/+3
2017-02-23Implement halt request.Tim Newsome1-24/+0
Also clean up some vestigial code.
2017-02-15Implement autoexec. DMI op 2 is just write now.Tim Newsome1-1/+2
Now passing MemTest{8,16,32,64}
2017-02-15Implement resume (untested).Tim Newsome1-0/+1
2017-02-13Implement program buffer preexec/postexec.Tim Newsome1-3/+8
I only tested preexec.
2017-02-13Abstract register read mostly working.Tim Newsome1-4/+42
Fails with not supported for 128-bit. Fails with exception (on rv32) with 64-bit. Succeeds (on rv32) with 32-bit.
2017-02-12Fix stack overflow and support --rbb-port=0Tim Newsome1-0/+1
2017-02-10Entering debug mode now jumps to "dynamic rom"Tim Newsome1-5/+30
2017-02-10Implement hartstatus field.Tim Newsome1-1/+4
2017-02-08Add writable ibuf and data registers.Tim Newsome1-0/+6
2017-02-08Serve up a correct dmcontrol register.Tim Newsome1-2/+7
2017-02-07OpenOCD does a dmi read and gets dummy value back.Tim Newsome1-0/+5
2016-05-23Turn off debugging.Tim Newsome1-4/+0
All the printfs would be pretty annoying if you're actually using this to debug something. Also fixed a small jump bug in halt.
2016-05-23Software breakpoints sort of work.Tim Newsome1-0/+14
2016-05-23Have Debug memory kind of working again.Tim Newsome1-5/+1
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23Refactor how we track in-progress operations.Tim Newsome1-0/+2
I think the functionality is unchanged.
2016-05-23Fix store to clear debug interrupt.Tim Newsome1-0/+1
2016-05-23Add debug_module bus device.Tim Newsome1-0/+37
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
generated by cgit v1.1 at 2024-08-07 02:25:06 +0000