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2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-10-04Fix remaining ignored-qualifiers warningAndrew Waterman1-1/+1
2022-09-20Merge pull request #1036 from plctlab/plct-sscofpmf-devAndrew Waterman1-0/+9
add support for sscofpmf extension v0.5.2
2022-08-11Unify PMPCFGx behaviour with PMPADDRx where PMP is disabled (#1068)Greg Chadwick1-0/+1
Previously any access to the PMPADDRx CSRs when no PMP regions were configured would result in an illegal instruction trap, whilst PMPCFGx registers would act as WARL, ignoring writes and reading as 0. This unifies the behaviour so both PMPADDRx and PMPCFGx CSRs produce an illegal instruction trap when accessed when no PMP regions are configured.
2022-08-09add support for sscofpmf extension v0.5.2Weiwei Li1-0/+9
since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently
2022-08-08Merge pull request #1059 from plctlab/plct-stateen-fixAndrew Waterman1-6/+0
add stateen related check to frm/fflags
2022-08-03Add Sstc support. (#1057)i2h21-1/+16
2022-08-03add stateen related check to frm/fflags and then apply to fcsr implicitlyWeiwei Li1-6/+0
2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman1-7/+10
Update for counter related CSR
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li1-0/+15
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li1-14/+2
2022-07-18Merge pull request #1041 from plctlab/plct-new-csrsAndrew Waterman1-0/+1
add support for m/henvcfgh and mconfigptr CSRs
2022-07-17extract the progress of computing the inital value of mstatus intoWeiwei Li1-0/+1
separate function compute_mstatus_initial_value()
2022-07-15Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmpAndrew Waterman1-0/+1
Conditionalize Smepmp extension (ePMP) support
2022-07-13Add proxy for accessing the low 32 bits of a 64-bit CSRScott Johnson1-0/+15
Use this for mstatus on RV32 so that `csrw mstatus` does not modify the bits in `mstatush`. Fixes #1044.
2022-07-13Remove no-longer-needed mask from rv32_high_csr_tScott Johnson1-1/+0
2022-07-13Remove unnecessary mask from rv32_high_csr_t constructorScott Johnson1-2/+2
2022-07-13Add verify_permissions() for mseccfg_csr_tYenHaoChen1-0/+1
The mseccfg only exists when enabling the Smepmp extension. If not enabling the Smepmp extension, CSR instructions to the mseccfg raise illegal instruction faults, and the PMP behaviors as hardwiring mseccfg 0 (the reset value of mseccfg).
2022-07-09add smstateen check for fcsr, senvcfg, henvcfgWeiwei Li1-0/+4
2022-07-09add standalone class for fcsr and senvcfg csrWeiwei Li1-0/+11
2022-07-09add support for csrs of smstateen extensionsWeiwei Li1-0/+19
2022-07-07modify mstatush_csr_t to general rv32_high_csr_tWeiwei Li1-4/+6
2022-07-07remove multi blank linesWeiwei Li1-37/+0
2022-05-11Change henvcfg csr to a henvcfg_csr_tRyan Buchner1-0/+14
To do so implemented henvcfg_csr_t. henvcfg.PBMTE will be read only 0 if menvcfg.PBMTE = 0.
2022-05-04Implement the new csr mseccfg for ePMP as dummysoberl@nvidia.com1-0/+16
2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-4/+1
Refactor trigger code
2022-04-04Refactor misa maskingMark Fedorov1-0/+1
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-4/+1
2022-03-16Inline most implicit accesses to fflags/frmAndrew Waterman1-1/+3
2022-03-15Rewrite sstatus_csr_t::enabled() for higher performanceAndrew Waterman1-2/+5
Eliminate calls to base_status_csr_t::enabled() so that the various read() calls can be inlined. Doing so also removes a redundant check of sstatus_write_mask. Schedule the most common exit path first.
2022-03-15Give concrete types to fields of sstatus_proxy_csr_tAndrew Waterman1-2/+2
Doing so allows calls to their members to be inlined.
2022-03-15Give concrete types to fields of sstatus_csr_tAndrew Waterman1-3/+4
Doing so allows calls to their members to be inlined.
2022-03-15Allow sstatus_proxy_csr_t::read() to be inlinedAndrew Waterman1-2/+6
2022-03-15Allow mstatus_csr_t::read() to be inlinedAndrew Waterman1-2/+6
2022-03-15Allow vsstatus_csr_t::read() to be inlinedAndrew Waterman1-2/+6
2022-03-15Move sstatus_proxy_csr_t defn below that of mstatus_csr_tAndrew Waterman1-11/+11
This will allow the former to depend on the latter in a future commit.
2022-03-15Fix perf regression from CSR refactoring (#949)Andrew Waterman1-3/+13
Since many instructions are only conditionally legal, their implementations need to query misa (or isa). Since reading misa is therefore on the critical path, make sure it's inlined. Making misa_csr_t a final class sidesteps the need for a vtable lookup when calling read().
2022-02-18Split out MINSTRET and MCYCLERupert Swarbrick1-4/+4
Before this change, the MCYCLE CSR was just a proxy for MINSTRET. Similarly, CYCLE was a proxy for INSTRET. This models a machine where every instruction takes exactly one cycle to execute. That's not quite precise enough if you want to do cosimulation: there, you're going to want to MCYCLE to actually match the behaviour of your processor (because you need reads from the relevant CSRs to give the expected result). This commit splits the two CSRs, leaving the other proxy relationships unchanged. The code in processor_t::step() which bumps MINSTRET now bumps MCYCLE by the same amount, maintaining the previous behaviour. Of course, now a cosimulation environment can update the value of MCYCLE to fix things up for multi-cycle instructions after they run.
2022-02-18Rename minstret CSR classes to something more generalRupert Swarbrick1-7/+7
No other functional change. This is preparation for a follow-up commit, which will split MINSTRET and MCYCLE (to allow cosimulation environments where the two values might not be equal)
2021-11-13Use enum to specify the 3 options for masking of intr CSRsScott Johnson1-2/+3
Because using two booleans gives the impression that there are four possibilities. Since hideleg is itself masked by mideleg, there are effectively only three choices, so make that explicit via enum.
2021-11-13Mask hideleg by midelegScott Johnson1-0/+9
According to spec clarification: https://github.com/riscv/riscv-isa-manual/pull/771 This has no functional effect today, because all the active bits of hideleg are tied to 1 inside mideleg.
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen1-2/+2
Krypto 1.0 changes: Entropy source CSR, name. List scalar crypto instruction groupings, as there is no single K extension. Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
2021-10-15Fix clang warningAndrew Waterman1-1/+1
2021-10-06Make vxsat into its own classScott Johnson1-0/+8
Since its rules will need to be different than other vector CSRs (coming next). No functional change intended.
2021-10-06Let each sstatus CSR determine extension enableScott Johnson1-0/+2
No functional change intended. This will allow me to consider whether the given field exists at all, which I will eventually use to fix #823.
2021-10-06Give sstatus_csr_t handles to its base_status_csr_t constituentsScott Johnson1-1/+6
So I can add specialized methods to base_status_csr_t next, for use from within sstatus_csr_t.
2021-09-29Convert vlenb to csr_tScott Johnson1-1/+1
Since it's constant, no new trace events will be seen.
2021-09-29Convert vstart to csr_tScott Johnson1-0/+5
Adds commit log events for vstart to many vector instructions.
2021-09-29Convert vxsat to csr_tScott Johnson1-0/+11
Adds commit log events for vxsat to many vector instructions.
2021-09-28Convert sentropy to csr_tScott Johnson1-0/+11
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