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Author
Files
Lines
2022-04-11
Merge pull request #944 from riscv-software-src/triggers
Scott Johnson
1
-56
/
+7
2022-04-11
Fix hgatp CSR write
Anup Patel
1
-1
/
+1
2022-04-06
mmu: support asid/vmid (#928)
Chih-Min Chao
1
-3
/
+8
2022-04-05
Merge pull request #960 from marcfedorow/upstream
Andrew Waterman
1
-6
/
+13
2022-04-05
Move num_triggers knowledge into triggers.h
Tim Newsome
1
-1
/
+1
2022-04-05
Don't access triggers vector directly from csrs.cc.
Tim Newsome
1
-4
/
+4
2022-04-05
Move tdata2 logic into trigger.
Tim Newsome
1
-6
/
+2
2022-04-05
Make misa.V writable
Mark Fedorov
1
-1
/
+3
2022-04-05
Since ca08503 this code only runs at reset, so no longer depends on misa.V be...
Mark Fedorov
1
-2
/
+2
2022-04-04
Make misa.Q writable
Mark Fedorov
1
-1
/
+3
2022-04-04
Refactor misa masking
Mark Fedorov
1
-3
/
+6
2022-03-30
Move tdata1 write logic into triggers.
Tim Newsome
1
-23
/
+1
2022-03-30
Move tdata1 read logic into triggers.cc.
Tim Newsome
1
-19
/
+1
2022-03-30
Move tdata2 into mcontrol_t
Tim Newsome
1
-9
/
+4
2022-03-30
Replace state.mcontrol with TM.triggers.
Tim Newsome
1
-3
/
+3
2022-03-30
mcontrol_match_t -> mcontrol_t::match_t
Tim Newsome
1
-1
/
+1
2022-03-30
Move mcontrol_t and mcontrol_match_t into triggers
Tim Newsome
1
-3
/
+3
2022-03-30
mcontrol_action_t -> triggers::action_t
Tim Newsome
1
-1
/
+1
2022-03-30
Implement Sv57 and Sv57x4 translation modes
Andrew Waterman
1
-1
/
+3
2022-03-30
Don't allow hgatp.MODE to be set to Sv48x4 unless implemented
Andrew Waterman
1
-2
/
+2
2022-03-16
Raise illegal (not virtual) instruction exception on counter writes (#951)
Andrew Waterman
1
-4
/
+1
2022-03-16
Refer to concrete members in sstatus_csr_t::dirty()
Andrew Waterman
1
-2
/
+2
2022-03-16
Speed up sstatus_csr_t::dirty(); remove redundant log entries
Andrew Waterman
1
-0
/
+6
2022-03-15
Rewrite sstatus_csr_t::enabled() for higher performance
Andrew Waterman
1
-11
/
+10
2022-03-15
Give concrete types to fields of sstatus_proxy_csr_t
Andrew Waterman
1
-1
/
+1
2022-03-15
Give concrete types to fields of sstatus_csr_t
Andrew Waterman
1
-1
/
+1
2022-03-15
Allow sstatus_proxy_csr_t::read() to be inlined
Andrew Waterman
1
-4
/
+0
2022-03-15
Allow mstatus_csr_t::read() to be inlined
Andrew Waterman
1
-5
/
+0
2022-03-15
Allow vsstatus_csr_t::read() to be inlined
Andrew Waterman
1
-4
/
+0
2022-03-15
Fix perf regression from CSR refactoring (#949)
Andrew Waterman
1
-9
/
+0
2022-03-12
Construct an isa_parser_t and pass it to processor_t constructor
Rupert Swarbrick
1
-2
/
+2
2022-02-23
csr: mstatus.sxl and mstatus.uxl are zero in rv32
Chih-Min Chao
1
-2
/
+3
2022-02-23
perf: refine csr accessibility checking
Chih-Min Chao
1
-2
/
+3
2022-02-18
Rename minstret CSR classes to something more general
Rupert Swarbrick
1
-13
/
+13
2021-12-16
TSR is read-only 0 when S-mode is not supported. (#890)
sven
1
-1
/
+2
2021-11-13
Use enum to specify the 3 options for masking of intr CSRs
Scott Johnson
1
-4
/
+3
2021-11-13
Mask hideleg by mideleg
Scott Johnson
1
-0
/
+10
2021-11-08
Move definitions of P and require macros
Andrew Waterman
1
-0
/
+2
2021-11-02
Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)
Markku-Juhani O. Saarinen
1
-6
/
+7
2021-10-14
Split 'P' to EXT_ZPN and friends (#830)
marcfedorow
1
-1
/
+1
2021-10-14
Call parent verify_permissions() for float_csr_t (#832)
Scott Johnson
1
-0
/
+1
2021-10-06
Disallow any insn jumping from Off to Dirty in mstatus.FS/XS/VS
Scott Johnson
1
-0
/
+4
2021-10-06
Allow vxsat to be accessed by P extension
Scott Johnson
1
-1
/
+1
2021-10-06
Make vxsat into its own class
Scott Johnson
1
-0
/
+17
2021-10-06
Allow instructions considering mstatus.FS/XS/VS to succeed when field doesn't...
Scott Johnson
1
-0
/
+2
2021-10-06
Let each sstatus CSR determine extension enable
Scott Johnson
1
-2
/
+6
2021-10-06
Give sstatus_csr_t handles to its base_status_csr_t constituents
Scott Johnson
1
-2
/
+4
2021-09-29
Modify logic for exception on writes to read-only CSRs
Scott Johnson
1
-1
/
+3
2021-09-29
Convert vlenb to csr_t
Scott Johnson
1
-2
/
+2
2021-09-29
Convert vstart to csr_t
Scott Johnson
1
-0
/
+6
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