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2022-04-11Merge pull request #944 from riscv-software-src/triggersScott Johnson1-56/+7
2022-04-11Fix hgatp CSR writeAnup Patel1-1/+1
2022-04-06mmu: support asid/vmid (#928)Chih-Min Chao1-3/+8
2022-04-05Merge pull request #960 from marcfedorow/upstreamAndrew Waterman1-6/+13
2022-04-05Move num_triggers knowledge into triggers.hTim Newsome1-1/+1
2022-04-05Don't access triggers vector directly from csrs.cc.Tim Newsome1-4/+4
2022-04-05Move tdata2 logic into trigger.Tim Newsome1-6/+2
2022-04-05Make misa.V writableMark Fedorov1-1/+3
2022-04-05Since ca08503 this code only runs at reset, so no longer depends on misa.V be...Mark Fedorov1-2/+2
2022-04-04Make misa.Q writableMark Fedorov1-1/+3
2022-04-04Refactor misa maskingMark Fedorov1-3/+6
2022-03-30Move tdata1 write logic into triggers.Tim Newsome1-23/+1
2022-03-30Move tdata1 read logic into triggers.cc.Tim Newsome1-19/+1
2022-03-30Move tdata2 into mcontrol_tTim Newsome1-9/+4
2022-03-30Replace state.mcontrol with TM.triggers.Tim Newsome1-3/+3
2022-03-30mcontrol_match_t -> mcontrol_t::match_tTim Newsome1-1/+1
2022-03-30Move mcontrol_t and mcontrol_match_t into triggersTim Newsome1-3/+3
2022-03-30mcontrol_action_t -> triggers::action_tTim Newsome1-1/+1
2022-03-30Implement Sv57 and Sv57x4 translation modesAndrew Waterman1-1/+3
2022-03-30Don't allow hgatp.MODE to be set to Sv48x4 unless implementedAndrew Waterman1-2/+2
2022-03-16Raise illegal (not virtual) instruction exception on counter writes (#951)Andrew Waterman1-4/+1
2022-03-16Refer to concrete members in sstatus_csr_t::dirty()Andrew Waterman1-2/+2
2022-03-16Speed up sstatus_csr_t::dirty(); remove redundant log entriesAndrew Waterman1-0/+6
2022-03-15Rewrite sstatus_csr_t::enabled() for higher performanceAndrew Waterman1-11/+10
2022-03-15Give concrete types to fields of sstatus_proxy_csr_tAndrew Waterman1-1/+1
2022-03-15Give concrete types to fields of sstatus_csr_tAndrew Waterman1-1/+1
2022-03-15Allow sstatus_proxy_csr_t::read() to be inlinedAndrew Waterman1-4/+0
2022-03-15Allow mstatus_csr_t::read() to be inlinedAndrew Waterman1-5/+0
2022-03-15Allow vsstatus_csr_t::read() to be inlinedAndrew Waterman1-4/+0
2022-03-15Fix perf regression from CSR refactoring (#949)Andrew Waterman1-9/+0
2022-03-12Construct an isa_parser_t and pass it to processor_t constructorRupert Swarbrick1-2/+2
2022-02-23csr: mstatus.sxl and mstatus.uxl are zero in rv32Chih-Min Chao1-2/+3
2022-02-23perf: refine csr accessibility checkingChih-Min Chao1-2/+3
2022-02-18Rename minstret CSR classes to something more generalRupert Swarbrick1-13/+13
2021-12-16TSR is read-only 0 when S-mode is not supported. (#890)sven1-1/+2
2021-11-13Use enum to specify the 3 options for masking of intr CSRsScott Johnson1-4/+3
2021-11-13Mask hideleg by midelegScott Johnson1-0/+10
2021-11-08Move definitions of P and require macrosAndrew Waterman1-0/+2
2021-11-02Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)Markku-Juhani O. Saarinen1-6/+7
2021-10-14Split 'P' to EXT_ZPN and friends (#830)marcfedorow1-1/+1
2021-10-14Call parent verify_permissions() for float_csr_t (#832)Scott Johnson1-0/+1
2021-10-06Disallow any insn jumping from Off to Dirty in mstatus.FS/XS/VSScott Johnson1-0/+4
2021-10-06Allow vxsat to be accessed by P extensionScott Johnson1-1/+1
2021-10-06Make vxsat into its own classScott Johnson1-0/+17
2021-10-06Allow instructions considering mstatus.FS/XS/VS to succeed when field doesn't...Scott Johnson1-0/+2
2021-10-06Let each sstatus CSR determine extension enableScott Johnson1-2/+6
2021-10-06Give sstatus_csr_t handles to its base_status_csr_t constituentsScott Johnson1-2/+4
2021-09-29Modify logic for exception on writes to read-only CSRsScott Johnson1-1/+3
2021-09-29Convert vlenb to csr_tScott Johnson1-2/+2
2021-09-29Convert vstart to csr_tScott Johnson1-0/+6
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