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2024-06-21Relax mstatus.vs dependency on full VJerry Zhao1-1/+2
2024-06-21Relax vector_csr dependency on 'V'Jerry Zhao1-4/+0
2024-06-21Relax has_fs dependency on misa.vJerry Zhao1-2/+1
isa_parser should already require any Zvef or Zved extensions imply F/D
2024-05-27Require vector extension when attempting vxsat writesrbuchner1-0/+2
Accidentally removed in c9468f6e02. See #1660.
2024-05-01Remove Zbpbo, Zpn, and Zpsfoperand implementationAndrew Waterman1-2/+0
2024-04-29Merge pull request #1648 from YenHaoChen/pr-hstateenAndrew Waterman1-5/+7
Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0
2024-04-29add hlvx pmp protect to fix issue 1557xinyuwang-sifive1-2/+2
2024-04-23Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0YenHaoChen1-5/+7
The specification states that writes to read-only bits in a RW CSR are ignored. The hstateen*[n] bits are read-only when mstateen*[n]=0. This PR proposes ignoring writes to read-only hstateen*[n] bits when mstateen*[n]=0 instead of writing the bits to 0.
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho1-0/+10
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name. 2. Add new software exception with tval 3 for shadow stack. 3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d. 4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding. 5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page. 6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag. 7. Check special pte(xwr=010) of SS page.
2024-04-09Ignore writes to henvcfg fields (PBMTE, STCE, and ADUE) when read-only 0YenHaoChen1-0/+5
The henvcfg fields, i.e., PBMTE, STCE, and ADUE, are read-only 0 when the corresponding bits in menvcfg are 0. Besides the reading behavior, the spec also specified the writing behavior, i.e., ignoring writes. This commit ignores writes to the henvcfg fields when read-only 0. Reference: https://github.com/riscv/riscv-isa-manual/issues/1312
2024-03-22Allow software check exception to be delegated from M mode regardless of ↵Ming-Yi Lai1-1/+1
Zicfilp being enabled
2024-03-06Zicfilp: Support delegating software check exception handlingMing-Yi Lai1-0/+1
2024-03-06Zicfilp: Preserve expected landing pad state on trapsMing-Yi Lai1-1/+3
2024-03-06Zicfilp: Add CSR fieldsMing-Yi Lai1-3/+16
2024-02-07Merge pull request #1591 from YenHaoChen/pr-sstc-stceAndrew Waterman1-2/+4
Teach Sstc to respect xenvcfg.STCE
2024-02-06Fix hvip.VSEIP and hvip.VSTIP, so they don't observe platform-specific ↵YenHaoChen1-0/+17
interrupts or CSR hgeip bits The H extension defines that bits VSEIP, VSTIP, and VSSIP of hvip are writable. (The other bits of hvip are read-only 0.) Only hip.VSSIP (mip.VSSIP) is an alias of hvip.VSSIP. The hip.VSEIP is the logical-OR of hvip.VSEIP, selected bit of hgeip by hstatus.VGEIN, and platform-specific external interrupt signals to VS-level, e.g., from AIA. The hip.VSTIP is the logical-OR of hvip.VSTIP and platform-specific timer interrupt signals to VS-level, e.g., from Sstc. Thus, the read values of hvip.VSEIP and hvip.VSTIP differ from the ones of hip.VSEIP and hip.VSTIP (mip.VSEIP and mip.VSTIP). In other words, the hvip isn't an alias (proxy) of mip. The current aliasing (proxy) implementation does not provide the desired behavior for hvip.VSEIP and hvip.VSTIP. An ISA-level behavior difference is that any platform-specific external and timer interrupt signals directed to VS-level should not be observable through the hvip. For instance, the hvip should not observe the virtual timer interrupt signal from the vstimecmp CSR (Sstc extension), which isn't true in the current implementation. Additionally, the hvip should not observe the virtual external interrupt signal from the IMSIC device (AIA extension). Another ISA-level behavior difference is that the hgeip and hstatus.VGEIN also should not affect hvip.VSEIP, which isn't true in the current implementation. This commit fixes the issue by giving the hvip a specialized class, hvip_csr_t. The hvip_csr_t aliases the hvip.VSSIP to the mip.VSSIP but decouples the hvip.VSEIP and hvip.VSTIP from mip.VSEIP and mip.VSTIP. Additionally, the commit updates the read value of mip to be the logical-OR of hvip.VSEIP, hvip.VSTIP, and other sources.
2024-02-06Teach Sstc to respect xenvcfg.STCEYenHaoChen1-2/+4
When menvcfg.STCE=0, mip.STIP reverts to its defined behavior as if unsupporting Sstc extension. When henvcfg.STCE=0, mip.VSTIP reverts to its defined behavior as if unsupporting Sstc extension. [https://github.com/riscv/riscv-time-compare/issues/5] The previous Sstc implementation does not respect the xenvcfg.STCE. In other words, the Sstc may assert mip.STIP (mip.VSTIP) when menvcfg.STCE=0 (henvcfg.STCE=0), which is a misbehaving.
2024-01-10fix merge issueVed Shanbhogue1-1/+0
2024-01-10fix merge issueVed Shanbhogue1-3/+0
2024-01-10Merge branch 'master' into zaamo_zalrscVed Shanbhogue1-0/+4
Signed-off-by: Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com>
2024-01-10Add Zaamo and Zalrsc extensionsVed Shanbhogue1-1/+7
2024-01-10B=Zba+Zbb+ZbsVed Shanbhogue1-1/+6
2024-01-04typo: HPM counters consider previous privilege mode if changedYenHaoChen1-1/+1
2023-12-30Add srmcfg CSRVed Shanbhogue1-0/+19
2023-11-29fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege ↵YenHaoChen1-4/+4
modes
2023-11-24stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in ↵YenHaoChen1-2/+6
HS-mode The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a mode other than M-mode. The previous implementation does not check the permission on accessing vstimecmp in HS-mode. This commit fixes the issue by moveing the permission check from virtualized_stimecmp_csr_t to stimecmp_csr_t, which implements the vstimecmp.
2023-07-26Add Smcntrpmf functionalityAtul Khare1-4/+43
If Smcntrpmf is enabled, mcycle / minstret increment only if counting for the privilege level isn't inhibited in mcyclecfg / minstretcfg.
2023-07-25Merge pull request #1383 from rivosinc/sscrind_featureAndrew Waterman1-0/+62
Add Smcsrind / Sscsrind support
2023-07-25legalize henvcfg.CBIEYenHaoChen1-1/+1
The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65
2023-07-25legalize senvcfg.CBIEYenHaoChen1-1/+1
The value 2 of senvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65
2023-07-25legalize menvcfg.CBIEYenHaoChen1-0/+13
The value 2 of menvcfg.CBIE is reserved. This commit legalizes it to 0 by adding a specialized class envcfg_csr_t. Reference: https://github.com/riscv/riscv-CMOs/issues/65
2023-07-19Add Smcsrind/Sscsrind supportAtul Khare1-0/+62
This adds the following CSRs: miselect (0x350), mireg (0x351), mireg2/3 (0x352, 0x353), mireg4-6 (0x355 - 0x357), siselect (0x150), sireg (0x151), sireg2/3 (0x152, 0x153), sireg4-6 (0x155 - 0x157), vsiselect (0x250), vsireg (0x251), mireg2/3 (0x252, 0x253), vsireg4-6 (0x255 - 0x257). Presently, attempts to read / write from ireg? registers will fail, and future extensions will provide proxy CSR mappings for the respective ?ireg CSRs.
2023-06-01dscr.ebreakh is now dcsr.ebreakv[su]Tim Newsome1-3/+6
This change was made ages ago in the spec. I did not actually test that the new privilege checks in ebreak and c.ebreak are correct, but all the existing debug tests still pass.
2023-05-25Implement dcsr.v and make DRET use itAndrew Waterman1-1/+7
Resolves #1365
2023-05-25Use more descriptive variable name in dcsr_csr_t::read; make it reg_tAndrew Waterman1-12/+12
2023-05-23Let mstatus.MPP initially be M-mode if unsupporting U-modeYenHaoChen1-0/+1
This commit lets the mstatus.MPP be a valid value if unsupporting U-mode. Without this commit, the mret may result in a corrupted state without properly setting the MPP to M-mode (if unsupporting U-mode).
2023-03-20Implement Smrnmi extensionAndrew Waterman1-0/+20
We don't model any sources of RNMI, so this is mostly vestigial.
2023-02-15Disable Zvfh when Zfhmin is disabledWeiwei Li1-1/+1
2023-02-15Disable Zvfh{min} when misa.V is clearedWeiwei Li1-0/+2
2023-02-15Disable Zfh{min} when misa.F is clearedWeiwei Li1-0/+2
2023-02-06Support dynamically disabling misa.C once againAndrew Waterman1-2/+15
Now, when misa.C is writable, clearing misa.C also disables any Zc* extension.
2023-02-06Make JVT CSR definition account for dynamically disabling ZcmtAndrew Waterman1-0/+3
No functional change yet.
2023-01-03Make misa.C read-onlyAndrew Waterman1-6/+1
This resolves the issue discussed in #1201. Prior to 0adf9307, clearing misa.C would disable compressed instructions and increase IALIGN to 32. Afterwards, clearing misa.C had essentially no effect because Zca and friends would stay enabled. While AFAICS this isn't technically incorrect, it certainly doesn't follow the principle of least surprise. Instead, remove the feature to toggle misa.C. The effect is that misa.C is 1 iff C is included in the ISA string, and IALIGN is independent of misa.C: specifically, IALIGN is 16 iff Zca is present. (And of course C implies Zca.) Removing the alignment check on misa writes is not a separate commit because these two changes should be made atomically. Not checking the alignment on misa writes goes hand-in-hand with misa.C being read-only.
2022-12-20Check commitlog-enable dynamicallly for csr_t::log_special_writeJerry Zhao1-4/+2
This incurs a negligible performance impact
2022-12-15Add config.h includes directly to source files instead of relying on header ↵Jerry Zhao1-0/+1
chaining This step is to ensure that removing config.h out of headers will not cause regressions.
2022-12-15Split decode.h into public decode.h and private decode_macros.hJerry Zhao1-1/+1
* decode.h contains constants/typedefs/classes. This should not depend on config.h * decode_macros.h contains internally used macros, and depends on config.h
2022-12-09triggers: implement tdata3 CSR fieldsYenHaoChen1-2/+2
2022-12-09refactor: add tdata3_csr_t; preparation for CSR textraYenHaoChen1-0/+12
2022-12-09refactor: remove proc parameter from functions of module_tYenHaoChen1-5/+5
2022-12-05clear mevent.VUINH and mevent.VSINH when misa.H is clearedYenHaoChen1-0/+4
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