| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-10-04 | Add UNUSED macro for suppressing unused-parameter/variable warnings | Andrew Waterman | 1 | -0/+2 | |
| 2022-07-18 | Fix load/store performance under clang | Andrew Waterman | 1 | -0/+2 | |
| Hopefully for the last time :-) | |||||
| 2021-07-28 | Add NORETURN macro | Andrew Waterman | 1 | -2/+4 | |
| 2020-11-18 | Only use __builtin_expect for __GNUC__ | Andrew Waterman | 1 | -2/+7 | |
| 2019-10-07 | Speed up compilation of disasm.cc, especially in clang | Andrew Waterman | 1 | -0/+2 | |
| 2013-03-25 | add BSD license | Andrew Waterman | 1 | -0/+2 | |
| 2013-02-12 | migrate to c++11 | Andrew Waterman | 1 | -2/+0 | |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+9 | |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -28/+0 | |
| 2011-05-29 | [sim,opcodes] improved sim build and run performance | Andrew Waterman | 1 | -0/+3 | |
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -0/+2 | |
| Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes. | |||||
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+23 | |
| Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/ | |||||
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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