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AgeCommit message (Expand)AuthorFilesLines
2014-01-20Merge branch 'confprec'Quan Nguyen45-0/+353
2013-12-17Speed things up quite a bitAndrew Waterman1-1/+1
2013-11-29Remove debug printf in vsetprecconfprecQuan Nguyen1-1/+0
2013-11-29Add vsetprec instruction prototypeQuan Nguyen5-0/+17
2013-11-25Update to new privileged ISAAndrew Waterman1-3/+0
2013-11-24Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEADQuan Nguyen2-2/+3
2013-11-21fix slli/slliw encoding bugYunsup Lee1-2/+2
2013-11-05correctly trap when SR_EA is disabledYunsup Lee1-0/+1
2013-11-04Fix declaration of half-precision instructionsAlbert Ou2-0/+2
2013-11-04Re-add Hwacha header fileAlbert Ou1-0/+1
2013-11-04Implement "half-baked" half-precision instruction subset for HwachaAlbert Ou39-2/+336
2013-10-28include stdexceptYunsup Lee1-0/+1
2013-10-21clarify vxcptsave/vxctkill semanticsYunsup Lee3-3/+7
2013-10-18implement vxcptsave/vxcptrestoreYunsup Lee4-3/+82
2013-10-18more hwacha supervisor stuffYunsup Lee6-17/+21
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee5-5/+223
2013-10-18can't execute frsr/fssr on utYunsup Lee3-4/+0
2013-10-18or into control thread's fp exceptionsYunsup Lee1-4/+0
2013-10-17catch trap_illegal_instruction in hwachaYunsup Lee1-0/+4
2013-10-17add hwacha exception supportYunsup Lee13-24/+209
2013-10-16fix maxvl calc logicYunsup Lee1-1/+5
2013-10-16use reset virtual methodYunsup Lee2-3/+4
2013-10-16use uint32_t for vlYunsup Lee1-1/+1
2013-10-16revamp hwacha; now runs in physical modeYunsup Lee242-259/+662
2013-07-26Remove more vector stuffAndrew Waterman1-0/+49
2013-07-26Rip out Hwacha for nowAndrew Waterman92-0/+219
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