rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2020-05-19	Add missing stdexcept imports	Schuyler Eldridge	1	-0/+1
	Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-10	op: update CSR	Chih-Min Chao	1	-2/+2
	1. add new hypervisor csr 2. add debug module csr 3. add some new high part register for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-05	When enabling the debug module, poll til it's really enabled	Andrew Waterman	1	-0/+2
	Resolves #435
2020-04-05	FESVR: ensure dmactive is 1 before reading debug module registers	Megan Wachs	1	-3/+3

2020-04-05	fixed htif exception typo (#423)	Dai chou	1	-1/+1

2020-02-12	FESVR: Can't read a DM register when DMACTIVE=0	Megan Wachs	1	-1/+1

2020-02-12	Support loading multiple ELF files via a new payload HTIF option	James Clarke	2	-7/+31
	Firmware implementations, such as OpenSBI's fw_jump, make use of this feature on other targets to avoid having to be rebuilt every time the payload is updated.
2020-02-12	Support plusarg +h/+help option for HTIF	James Clarke	2	-1/+6

2020-02-12	Allow EM_NONE ELFs, too	Andrew Waterman	2	-1/+3

2020-02-12	Refuse to load non-EXEC/non-RISC-V/non-V1 ELFs (#388)	Alexander Lent	2	-0/+10
	Stricter validation of ELF binaries improves usability with informative assertions. This prevents users from loading ELF relocatable files and binaries compiled for their (non-RISC-V) workstations, for example. Without this patch, spike would attempt to load nearly any ELF given, but it would usually fail with an error about debug module accesses, since the given ELF causes accesses in the debug module's memory space. Even if spike successfully loaded the ELF file, it would still misbehave during simulation, for example in the case of ELF relocatable files. ELF magic numbers come from official ELF documents: TIS ELF spec v1.2, via Linux Foundation Referenced Specifications See: https://refspecs.linuxbase.org/ RISC-V magic number comes from official RISC-V ELF documents: See: riscv/riscv-elf-psabi-doc@60c25981b62c0b43d16142f8a12c8b1e98e60d4d
2019-10-29	Whithhold BE ELF loading until BE target support is available	Marcus Comstedt	1	-9/+3

2019-10-29	Implement support for big-endian hosts	Marcus Comstedt	4	-40/+52
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-07-22	Add override modifier to fix clang warnings	Andrew Waterman	1	-2/+2

2019-05-14	fesvr: remove duplicated encoding	Chih-Min Chao	1	-1471/+0
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-14	Build fesvr as -fPIC to improve compatibility with old uses	Andrew Waterman	1	-0/+2

2019-05-14	Add fesvr; only globally install fesvr headers/libs	Andrew Waterman	34	-0/+6394