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The shift amount is 6 bits wide on RV64. As with the base ISA shifts, we
ignore XLEN and unconditionally disassemble the 6-bit immediate on RV32.
Partially reverts da93bdc435b985fd354e01c26470f64c33cecaa6
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Iterate over the instruction chains in reverse order, prioritizing
the last call to `disassembler_t::add_insn`.
To preserve behavior for the standard instructions, reverse the order
in which we add instructions in the `disassembler_t` constructor.
Supersedes #995.
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We do not condition them on Zicbop/Zihintpause because,
definitionally, all implementations provide them.
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These affect the "max_isa" value (now exposed as get_max_isa()) and
feel like they're similar to the other computations done in
isa_parser_t.
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No functional change, but this is needed for a following refactor
where we're passing it around const.
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Before this patch, spike just had an "Xbitmanip" extension which
covered everything in the proposed bitmanip extension that hadn't been
ratified. The problem is that if you want to model (or verify) a
processor that targetted just some of the proposed bitmanip extension,
you couldn't configure Spike to do that.
For example, the lowRISC Ibex processor has several different
configurations. The "balanced" configuration targetted Zba, Zbb, Zbs,
Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified,
we'll now be able to use an ISA string like
rv32imc_Zba_Zbb_Zbs_XZbf_XZbt
and Spike will correctly fail to decode instructions like 'bcompress',
which would have been decoded with Xbitmanip.
This patch adds a new custom extension name for each part of the
extension that wasn't fully ratified. These have an 'X' prefix so, for
example, the bit permutation instructions that were proposed as Zbp
can be found under XZbp.
Specifying "Xbitmanip" gets all of these extensions, so its behaviour
should be unchanged.
Note that the slo(i) / sro(i) instructions have been moved from the
proposed Zbb to XZbp. This matches a comment in the Change History
section of v0.93 of the bitmanip spec: it seems that the authors
forgot to also move them in Table 2.1 (which gives the lists of
instructions for each extension). This change won't break anything
that currently exists, but it took quite a while to figure out what
was going on so I thought I'd leave a breadcrumb trail for the next
engineer!
The bulk of the patch is just defining some more entries in the
isa_extension_t enum and rewriting each of the instructions to depend
on the relevant entry. This is mostly a straight textual replacement
but it's slightly more complicated for things like the "pack"
instruction that are defined by several different proposed extensions.
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into plctlab-plct-cmo-upstream
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It's helpful to attempt to disassemble instructions for disabled
extensions, so attempt to do so. Since some extensions conflict
in the opcode space, continue to give higher priorty to explicitly
enabled extensions.
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Resolves #916
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Refer to rvv-spec v1.0-rc2
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Now it disassembles 0x0000 (invalid encoding of c.addi4spn) as c.unimp
(RVC). Non-RVC variant of unimp pseudoinstruction (0xc0001073) is also
implemented.
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Krypto 1.0 changes: Entropy source CSR, name.
List scalar crypto instruction groupings, as there is no single K extension.
Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
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Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
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Stringstream is very slow, so avoid using it in cases where simply
using a string doesn't make the code too ugly.
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Optimize the hash functions for RISC-V instruction encodings. This is
only a perf optimization; instructions that don't adhere to RISC-V
standard practice will still disassemble correctly, just more slowly.
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* Added ZMMUL extension
* Splitted P-ext to its zeds
* Typo fix
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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SWAP16 is an alias to PKBT16 since p-spec v0.9.3.
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Factor out most common instruction patterns into functions, so tha
much less static code needs to be compiled.
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Precompiled headers were broken because they weren't compiled with
the same -fPIC setting as the rest of the code. Fix by just making
everything use -fPIC.
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- Remove remaining code which allowed spike to differentiate between
RV32 and RV64 instructions which share an encoding.
On branch scalar-crypto
Changes to be committed:
modified: disasm/disasm.cc
modified: riscv/processor.cc
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* Priv virtual memory updates
* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set
* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)
* Add Svinval instructions
Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...
If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.
* Svinval: use #include rather than copying code
..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions
Thanks to @aswaterman for the suggestion
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They have been remove in 0.10 spec
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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* rvp: add 8/16 bits add/sub simd instructions
* rvp: add 8/16 bits shift simd instructions
* rvp: add 8/16 bits compare simd instructions
* rvp: add 8/16 bits multiply simd instructions
* rvp: add 8/16 bits misc simd instructions
* rvp: add 8 bits unpacking simd instructions
* rvp: update suppported extention and add restriction
* rvp: update encoding.h and riscv.mk.in
* rvp: disasm: add simd instruction support
* rvp: update readme for p-ext simd instructions
* rvp: fix rvp support version
* rvp: update encoding.h generated from riscv-opcode p-ext branch
* rvp: rename some macro argument
* rvp: add pk[bb,bt,tt,tb][16,32] instructions
* rvp: add kadd32, [su]maqa[_su] instructions
* rvp: fix missing initial value of pd
* rvp: add msw 32x32 multiply & add instructions
* rvp: change to use extract64
* rvp: add msw 32x16 multiply & add instructions
* rvp: fix some style
* rvp: change reduction marcro definition
* rvp: add signed 16x32 add/subtract instructions
* rvp: use stdint to replace hardcode max/minimum
* rvp: refactor some p-ext macro code
* rvp: add partial simd miscellaneous instructions
* rvp: add signed 16 x 64 add/subtract Instructions
* rvp: add 64-bit add & sub instructions
* rvp: add 32-bit mul with 64-bit add/sub instructions
* rvp: add 16-bit mul with 64-bit add/sub instructions
* rvp: disasm: add 64 bit profile instruction support
* rvp: add Q15 saturation instructions
* rvp: fix kmar64/kmsr64 saturation behavior
* rvp: add 32-bit computation instructions
* rvp: add rdov/clrov and fix khm16 behavior of setting OV flag
* rvp: add non simd miscellaneous instructions
* rvp: add Q31 saturation instructions
* rvp: disasm: add non-simd instruction support
* rvp: add 32 bits add/sub simd instructions
* rvp: fix left shift saturation bug
* rvp: add 32 bits shift simd instructions
* rvp: add rv64 only Q15 simd instructions
* rvp: add rv64 only 32-bit multiply instructions
* rvp: add rv64 only 32-bit miscellaneous instructions
* rvp: add rv64 only 32-bit mul & add instructions
* rvp: add rv64 only 32-bit parallel mul & add instructions
* rvp: add rv64 only non-simd 32-bit shift instructions
* rvp: disasm: remove redundant tab
* rvp: disasm: add rv64 only instructions support
* rvp: change ov csr to ucode to match v0.5.2 spec
* rvp: update readme for p-ext 0.5.2
* rvp: update to p-ext v0.9.1
* rvp: update to p-ext v0.9.2
* rvp: update readme for p-ext 0.9.2
* rvp: fix macro for PKxx16 & PKxx32 commands.
* rvp: fix missing for in PKxxdd macro
* Sign-extension for p-ext insns
* * Fixed uclipNN insns while sh >> 64 is an UB.
* Added missing OV
* Added missing sext_xlen
* Remove unused macroses
* Sign extension for RD_PAIR macro
* rvp: remove lost tab
Co-authored-by: Mark Fedorov <mark.fedorov@cloudbear.ru>
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Scalar crypto fixes
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Historically, one could uniquely decode any RISC-V instruction based on
the instruciton to decode, plus a MATCH and MASK pair.
The scalar crypto extension adds instructions for accelerating the AES
algorithm which work very differently on RV32 and RV64. However, they
overlap in terms of opcodes. The instructions are always mutually
exclusive, and so it makes sense to overlap them this way to save
encoding space.
This exposed a problem, where previously Spike assumed the decoder
function was something like:
> decode(instr_word, MATCH, MASK)
Now it needed to be
> decode(instr_word, MATCH, MASK, current_xlen)
To get around this in the initial implementation, the instructions which
shared opcodes were implemented in the same *.h file - e.g. aesds.h
contained an implementation of aes32dsi, and aes64ds. We detected
xlen in the file, and executed the appropriate instruction logic.
This worked fine for our limited set of benchmarks.
After more extensive testing, we found that Spike has an optimisation
which changes the order in which it tries to decode instructions based
on past instructions.
Running more extensive tests exposed the fact that the decoding logic
could still not unambiguously decode the instructions. Hence, more
substantial changes were needed to tell spike that an instruction is
RV32 or RV64 only.
These changes have been implemented as part of
- riscv/encoding.h
- disasm/disasm.cc
- riscv/processor.cc/h
Basically, every instr_desc_t has an extra field which marks which
base architecture the instruction can be exectuted on. This bitfield
can be altered for particular instructions.
The changes to riscv/insns/* simply split out the previously combined
instructions into a separate header files.
On branch scalar-crypto-fix
Changes to be committed:
modified: disasm/disasm.cc
modified: riscv/encoding.h
new file: riscv/insns/aes32dsi.h
new file: riscv/insns/aes32dsmi.h
new file: riscv/insns/aes32esi.h
new file: riscv/insns/aes32esmi.h
new file: riscv/insns/aes64ds.h
new file: riscv/insns/aes64dsm.h
new file: riscv/insns/aes64es.h
new file: riscv/insns/aes64esm.h
deleted: riscv/insns/aesds.h
deleted: riscv/insns/aesdsm.h
deleted: riscv/insns/aeses.h
deleted: riscv/insns/aesesm.h
modified: riscv/processor.cc
modified: riscv/processor.h
modified: riscv/riscv.mk.in
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Since we don't support RV128
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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(#611)
ref:
https://github.com/riscv/riscv-v-spec/commit/511d0b84a3848de437fd01990d078feaa2871b11
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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