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rocket-tools/riscv-gnu-toolchain/spike.git
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cs250
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debug_rom
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dts_parsing
dynamic
eos18-bringup
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sifive/rvv0.9-phase2
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debug_rom.h
Age
Commit message (
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Author
Files
Lines
2017-04-17
debug: Use a more practical debug ROM
Megan Wachs
1
-14
/
+9
2016-09-02
Rebuild debug ROM because CSR encoding changed.
Tim Newsome
1
-2
/
+2
2016-06-22
Parameterize debug ROM contents on XLEN
Andrew Waterman
1
-14
/
+11
2016-06-09
Fix 2 bugs in Debug ROM: (#52)
Tim Newsome
1
-5
/
+5
2016-06-03
DCSR cause was moved, bug debug ROM wasn't updated
Tim Newsome
1
-1
/
+1
2016-06-01
Move sethaltnot and cleardebint.
Tim Newsome
1
-2
/
+2
2016-05-24
New encoding.h for new CSR addresses.
Tim Newsome
1
-4
/
+4
2016-05-24
Move cleardebint, per spec.
Tim Newsome
1
-2
/
+2
2016-05-23
Change DCSR bits to match spec.
Tim Newsome
1
-3
/
+3
2016-05-23
Use fence.i in Debug ROM.
Tim Newsome
1
-9
/
+9
2016-05-23
Add dret.
Tim Newsome
1
-1
/
+1
2016-05-23
Implement single memory read access.
Tim Newsome
1
-16
/
+17
2016-05-23
Exceptions in Debug Mode, stay in Debug Mode.
Tim Newsome
1
-15
/
+16
2016-05-23
Have Debug memory kind of working again.
Tim Newsome
1
-8
/
+8
2016-05-23
Fix race using fence.
Tim Newsome
1
-16
/
+15
2016-05-23
processor_t unfriends gdbserver_t.
Tim Newsome
1
-1
/
+1
2016-05-23
Add debug_module bus device.
Tim Newsome
1
-4
/
+4
2016-05-23
ROM -> RAM -> ROM, waiting for debug int.
Tim Newsome
1
-1
/
+1
2016-05-23
Jump to the correct (temporary) Debug RAM address.
Tim Newsome
1
-5
/
+5
2016-05-23
Clean up how Debug ROM is included.
Tim Newsome
1
-0
/
+18