rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2017-04-18	debug: Add fence and fence.i to ensure Debug RAM is ready.	Megan Wachs	1	-4/+5

2017-04-17	debug: Use a more practical debug ROM	Megan Wachs	1	-14/+9

2016-09-02	Rebuild debug ROM because CSR encoding changed.	Tim Newsome	1	-2/+2

2016-06-22	Parameterize debug ROM contents on XLEN	Andrew Waterman	1	-14/+11

2016-06-09	Fix 2 bugs in Debug ROM: (#52)	Tim Newsome	1	-5/+5
	1. Debug ROM wasn't actually writing 0xffffffff to the last word in Debug RAM after an exception happened. 2. Fix a race where debug interrupts were cleared before that write would have happened, so a debugger (gdbserver.cc in this case) might get the wrong idea about whether an exception happened or not. Why wasn't this wreaking havoc before?
2016-06-03	DCSR cause was moved, bug debug ROM wasn't updated	Tim Newsome	1	-1/+1
	As a result Debug ROM would always take the spontaneous halt code path. This didn't hurt spike since (so far?) the spike debug handler doesn't attempt to do anything quick while code is running. But now the ROM is more correct.
2016-06-01	Move sethaltnot and cleardebint.	Tim Newsome	1	-2/+2
	Now it matches Krste's memory map.
2016-05-24	New encoding.h for new CSR addresses.	Tim Newsome	1	-4/+4

2016-05-24	Move cleardebint, per spec.	Tim Newsome	1	-2/+2

2016-05-23	Change DCSR bits to match spec.	Tim Newsome	1	-3/+3
	Cleaned up debug ROM code a little.
2016-05-23	Use fence.i in Debug ROM.	Tim Newsome	1	-9/+9
	This replaces a hack that just disabled all of the icache.
2016-05-23	Add dret.	Tim Newsome	1	-1/+1

2016-05-23	Implement single memory read access.	Tim Newsome	1	-16/+17
	Prevent unaligned accesses in memory read. Also change how exceptions in Debug Mode are signaled.
2016-05-23	Exceptions in Debug Mode, stay in Debug Mode.	Tim Newsome	1	-15/+16
	Now things don't blow up when reading a non-existent CSR.
2016-05-23	Have Debug memory kind of working again.	Tim Newsome	1	-8/+8
	Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
2016-05-23	Fix race using fence.	Tim Newsome	1	-16/+15

2016-05-23	processor_t unfriends gdbserver_t.	Tim Newsome	1	-1/+1

2016-05-23	Add debug_module bus device.	Tim Newsome	1	-4/+4
	This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
2016-05-23	ROM -> RAM -> ROM, waiting for debug int.	Tim Newsome	1	-1/+1

2016-05-23	Jump to the correct (temporary) Debug RAM address.	Tim Newsome	1	-5/+5

2016-05-23	Clean up how Debug ROM is included.	Tim Newsome	1	-0/+18
	I'm not thrilled about including a static copy in so many cc files, and making the compiler throw it out. But without really grokking the Makefile this is the best it's going to be.