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2019-10-28Implement support for big-endian hostsMarcus Comstedt1-1/+1
2019-09-02Fix OSX buildAndrew Waterman1-1/+3
Closes #326
2019-07-22Implement MMIO device plugins.Aaron Jones1-0/+1
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-2/+1
2019-06-14rvv: add configuration and command-line optionChih-Min Chao1-0/+7
1. configure option "--with-varch" the option defines the default u-arch implementatiton-decided parameter VLEN: vector register length in bit SLEN: striping distance in bit ELEN: max element size in bit ex: --with-vector=v128:e32:s128 2. add __int128_t type checking 3. add --varch command option and help message ex: --varch=v512:e64:s512 Signed-off-by: Dave Wen <dave.wen@sifive.com>
2019-03-31Add fesvr; only globally install fesvr headers/libsstatic-linkAndrew Waterman1-1/+2
2017-06-05Configure should fail if device-tree-compiler is not installedAndrew Waterman1-1/+2
Fixes #107
2017-03-21autoconf: put location of 'dtc' into config.hWesley W. Terpstra1-0/+2
2016-03-02Add autoconf check for little-endiannessAndrew Waterman1-0/+2
2016-03-02Compile debug symbolsAndrew Waterman1-2/+2
2016-01-24Remove hwacha supportAndrew Waterman1-2/+1
Support for hwacha will continue on the ESP branch (see https://github.com/ucb-bar/esp-isa-sim).
2015-05-13Install pkg-config files for SpikePalmer Dabbelt1-0/+6
The actual Spike package consists of a whole bunch of libraries. This installs a pkg-config file for each generated library, and a meta pkg-config file (riscv-spike.pc) that links in all the other Spike libraries except dummy_rocc (which I figure isn't interesting). This allows me to package and install spike, and then use that package to build an extension library (so I don't have to fork Spike for my own ISA extension).
2015-04-09Fix autoconf for RHEL6Andrew Waterman1-1/+1
2015-01-09Don't look for a simulator when cross compilingAndrew Waterman1-1/+0
2014-12-20Support building from within root directoryAndrew Waterman1-1/+1
2014-11-25Factor out the dummy RoCC acceleratorAndrew Waterman1-1/+1
2014-11-19Suppress harmless warningsAndrew Waterman1-2/+2
specifically, unused variables in auto-generated code.
2014-01-26Eliminate hwacha <-> riscv circular dependenceAndrew Waterman1-1/+1
We now split out the spike executable into another subproject, which depends on both rocket and hwacha
2014-01-25Merge softfloat_riscv into softfloatAndrew Waterman1-1/+1
They really aren't independent libraries.
2014-01-24Build and use shared libraries onlyAndrew Waterman1-1/+2
2013-10-16revamp hwacha; now runs in physical modeYunsup Lee1-1/+1
2013-08-11Instructions are no longer member functionsAndrew Waterman1-1/+1
2013-05-13change riscv-isa-run to spikeYunsup Lee1-1/+1
2013-02-12migrate to c++11Andrew Waterman1-1/+1
2013-01-25change htif to link against libfesvrAndrew Waterman1-1/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+103
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-103/+0
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-1/+1
2010-08-18[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2bAndrew Waterman1-1/+1
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman1-1/+1
The intersection of the Hauser FP and MIPS FP is implemented.
2010-07-18Reorganized directory structureAndrew Waterman1-0/+103
Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/