Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-03-04 | rvv: remove the option of vector impl. check | Zhen Wei | 1 | -3/+0 | |
The check is not needed anymore since most vector kernels are supported in current implemented vector instruction set. | |||||
2019-11-17 | Add --priv option to control which privilege modes are available | Andrew Waterman | 1 | -0/+3 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-09-04 | rvv: reimplement check-1905 as check-impl | Chih-Min Chao | 1 | -2/+2 | |
build with --enable-check-imple run with --check-impl=1905 (or 1905 or future release) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-05-19 | rvv: add --enable-1905-check | Chih-Min Chao | 1 | -0/+3 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-04-30 | rvv: configurable vector architecture during configuration and | Dave.Wen | 1 | -0/+3 | |
execution time configuration: --with-vector ${VARCH_STR} execution: --varch ${VARCH_STR} VARCH_STR representation: v${VLEN in bits}:e${ELEN in bits}:s${SLEN in bits} e.g.: v128:e32:s128 | |||||
2017-04-05 | Add --enable-misaligned option for misaligned ld/st support | Andrew Waterman | 1 | -0/+3 | |
Resolves #93 | |||||
2017-03-21 | autoconf: put location of 'dtc' into config.h | Wesley W. Terpstra | 1 | -0/+3 | |
2017-02-18 | Make HW setting of PTE A/D bits optional (by configure arg) | Andrew Waterman | 1 | -0/+3 | |
https://github.com/riscv/riscv-isa-manual/issues/14 | |||||
2016-04-02 | Allow configuration of default ISA with --with-isa | Andrew Waterman | 1 | -2/+44 | |
2015-04-03 | Support setting ISA/subsets with --isa flag | Andrew Waterman | 1 | -9/+0 | |
Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha | |||||
2015-03-30 | Implement RVC draft | Andrew Waterman | 1 | -0/+3 | |
2014-12-29 | autoreconf 65ba70071d11cc19b3dc85c047c5fea6d4d7bc0d | Palmer Dabbelt | 1 | -4/+1 | |
2014-11-25 | Factor out the dummy RoCC accelerator | Andrew Waterman | 1 | -0/+3 | |
2014-08-15 | Added PC histogram option. | Christopher Celio | 1 | -0/+3 | |
- Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag. | |||||
2014-01-26 | Enable runtime loading of dynamic library with --extlib | Andrew Waterman | 1 | -1/+1 | |
2014-01-24 | Require libdl for dynamic linking at runtime | Andrew Waterman | 1 | -0/+3 | |
2013-10-17 | add hwacha exception support | Yunsup Lee | 1 | -0/+3 | |
2013-10-10 | commit configure script; new configure option --enable-commitlog | Yunsup Lee | 1 | -0/+3 | |
2013-07-26 | Remove more vector stuff | Andrew Waterman | 1 | -6/+0 | |
2013-01-25 | change htif to link against libfesvr | Andrew Waterman | 1 | -0/+6 | |
2011-11-11 | Remove dependence on binutils | Your Name | 1 | -3/+0 | |
We now have our own disassembler. | |||||
2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+46 | |
2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -49/+0 | |
2011-04-15 | [sim] added icache simulator (disabled by default) | Andrew Waterman | 1 | -0/+3 | |
2011-04-09 | [sim] add disable option for vector | Yunsup Lee | 1 | -0/+3 | |
2011-04-09 | [sim,pk] reorganized status register | Andrew Waterman | 1 | -0/+3 | |
2010-10-15 | [pk, sim] added FPU emulation support to proxy kernel | Andrew Waterman | 1 | -0/+6 | |
2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -0/+6 | |
2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+28 | |
Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/ |