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With recent compilers on recent computers, the much simpler version of
the code is actually slightly faster. I suspect, but haven't proven,
that more accurate indirect jump prediction is the main explanation.
Reduced I$ pressure might be a secondary factor.
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The B extension still implies the presence of Zba/Zbb/Zbc/Zbs.
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Co-authored-by: zhongcy <zhongcy93@gmail.com>
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This is a bug in the spec that will be changed in the next few days.
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For V=0 or V=1 writes to satp, the entire write is suppressed if the
MODE is not supported.
For V=0 writes to vsatp, only normal WARLness applies.
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hgatp.PPN should be writable even if the new MODE is invalid.
Additionally, mask off the two LSBs, as the spec allows.
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* rvp: add 8/16 bits add/sub simd instructions
* rvp: add 8/16 bits shift simd instructions
* rvp: add 8/16 bits compare simd instructions
* rvp: add 8/16 bits multiply simd instructions
* rvp: add 8/16 bits misc simd instructions
* rvp: add 8 bits unpacking simd instructions
* rvp: update suppported extention and add restriction
* rvp: update encoding.h and riscv.mk.in
* rvp: disasm: add simd instruction support
* rvp: update readme for p-ext simd instructions
* rvp: fix rvp support version
* rvp: update encoding.h generated from riscv-opcode p-ext branch
* rvp: rename some macro argument
* rvp: add pk[bb,bt,tt,tb][16,32] instructions
* rvp: add kadd32, [su]maqa[_su] instructions
* rvp: fix missing initial value of pd
* rvp: add msw 32x32 multiply & add instructions
* rvp: change to use extract64
* rvp: add msw 32x16 multiply & add instructions
* rvp: fix some style
* rvp: change reduction marcro definition
* rvp: add signed 16x32 add/subtract instructions
* rvp: use stdint to replace hardcode max/minimum
* rvp: refactor some p-ext macro code
* rvp: add partial simd miscellaneous instructions
* rvp: add signed 16 x 64 add/subtract Instructions
* rvp: add 64-bit add & sub instructions
* rvp: add 32-bit mul with 64-bit add/sub instructions
* rvp: add 16-bit mul with 64-bit add/sub instructions
* rvp: disasm: add 64 bit profile instruction support
* rvp: add Q15 saturation instructions
* rvp: fix kmar64/kmsr64 saturation behavior
* rvp: add 32-bit computation instructions
* rvp: add rdov/clrov and fix khm16 behavior of setting OV flag
* rvp: add non simd miscellaneous instructions
* rvp: add Q31 saturation instructions
* rvp: disasm: add non-simd instruction support
* rvp: add 32 bits add/sub simd instructions
* rvp: fix left shift saturation bug
* rvp: add 32 bits shift simd instructions
* rvp: add rv64 only Q15 simd instructions
* rvp: add rv64 only 32-bit multiply instructions
* rvp: add rv64 only 32-bit miscellaneous instructions
* rvp: add rv64 only 32-bit mul & add instructions
* rvp: add rv64 only 32-bit parallel mul & add instructions
* rvp: add rv64 only non-simd 32-bit shift instructions
* rvp: disasm: remove redundant tab
* rvp: disasm: add rv64 only instructions support
* rvp: change ov csr to ucode to match v0.5.2 spec
* rvp: update readme for p-ext 0.5.2
* rvp: update to p-ext v0.9.1
* rvp: update to p-ext v0.9.2
* rvp: update readme for p-ext 0.9.2
* rvp: fix macro for PKxx16 & PKxx32 commands.
* rvp: fix missing for in PKxxdd macro
* Sign-extension for p-ext insns
* * Fixed uclipNN insns while sh >> 64 is an UB.
* Added missing OV
* Added missing sext_xlen
* Remove unused macroses
* Sign extension for RD_PAIR macro
* rvp: remove lost tab
Co-authored-by: Mark Fedorov <mark.fedorov@cloudbear.ru>
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At compile time, gcc complains with:
../riscv/processor.cc:787:94: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 5 has type ‘uint64_t {aka long unsigned int}’ [-Wformat=]
The variable 'bits' is an uint64_t, so that PRIx64 should be used to print it out.
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* Implement JTAG BYPASS register.
This allows spike to put into a virtual scan chain with other
remote_bitbang JTAG devices.
* Initialize bypass to 0.
Also change what we do on what edge. In theory that's more correct but
in practice it doesn't make a difference.
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* make value display depend on max_xlen
* try to make spike look for correct pk
* PRIx64 instead of PRIx32, TARGET_ARCH back to 64
* 32 bit memory data, exception epc and tval
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(#690)
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Fix `stx_ino` member name in commit b65ead8
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Need to sign-extend result.
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Was broken by #681.
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Add `statx` syscall to Spike
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HS-level interrupts should always be enabled when in VS-mode
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See https://github.com/riscv/riscv-isa-manual/issues/633
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We can use the nullness of pointers to indicate RV32-only or RV64-only
instructions, rather than a new field dedicated to that purpsoe.
The bug fix is that the new field wasn't always initialized; now,
it doesn't need to be.
Resolves #673
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Otherwise, mstatus.MPV and hstatus.SPV could remain 1, and executing
mret/sret would then set state.v=1, which would be bad since
hypervisor's supposed to be disabled.
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Which I will reuse next.
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Scalar crypto fixes
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Since this is not modifiable in the real sstatus, so it should not be
in the virtualized version either.
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* Simplify Boolean logic
No functional change intended.
* Apply same logic to virtualize sstatus.XS as used for VS and FS
Though this macro does not seem to be used anywhere today.
* Extract common macro to DRY up code
* Dirty both mstatus and vsstatus FP fields
Fixes https://github.com/riscv/riscv-isa-sim/issues/660
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* Don't make MPRV load/store virtual if MPV=1, MPP=3
* Use PRV_M instead of the value "3"
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Table 5.2 requires certain bits to be writable in hedeleg:
https://github.com/riscv/riscv-isa-manual/blob/0453d462a180927169656e6e3f7faf3042b23e5b/src/hypervisor.tex#L386-L409
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The priv spec says: "For example, the value of the HS-level sstatus.FS
[aka mstatus.FS] does not affect vsstatus.SD."
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It was reading as 0, which is not a legal value.
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It was reading as 0, which is not a legal value.
In mstatus, UXL gets initialized by the call to set_csr(CSR_MSTATUS)
here in processor_t::reset().
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Rvv v0.10
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Historically, one could uniquely decode any RISC-V instruction based on
the instruciton to decode, plus a MATCH and MASK pair.
The scalar crypto extension adds instructions for accelerating the AES
algorithm which work very differently on RV32 and RV64. However, they
overlap in terms of opcodes. The instructions are always mutually
exclusive, and so it makes sense to overlap them this way to save
encoding space.
This exposed a problem, where previously Spike assumed the decoder
function was something like:
> decode(instr_word, MATCH, MASK)
Now it needed to be
> decode(instr_word, MATCH, MASK, current_xlen)
To get around this in the initial implementation, the instructions which
shared opcodes were implemented in the same *.h file - e.g. aesds.h
contained an implementation of aes32dsi, and aes64ds. We detected
xlen in the file, and executed the appropriate instruction logic.
This worked fine for our limited set of benchmarks.
After more extensive testing, we found that Spike has an optimisation
which changes the order in which it tries to decode instructions based
on past instructions.
Running more extensive tests exposed the fact that the decoding logic
could still not unambiguously decode the instructions. Hence, more
substantial changes were needed to tell spike that an instruction is
RV32 or RV64 only.
These changes have been implemented as part of
- riscv/encoding.h
- disasm/disasm.cc
- riscv/processor.cc/h
Basically, every instr_desc_t has an extra field which marks which
base architecture the instruction can be exectuted on. This bitfield
can be altered for particular instructions.
The changes to riscv/insns/* simply split out the previously combined
instructions into a separate header files.
On branch scalar-crypto-fix
Changes to be committed:
modified: disasm/disasm.cc
modified: riscv/encoding.h
new file: riscv/insns/aes32dsi.h
new file: riscv/insns/aes32dsmi.h
new file: riscv/insns/aes32esi.h
new file: riscv/insns/aes32esmi.h
new file: riscv/insns/aes64ds.h
new file: riscv/insns/aes64dsm.h
new file: riscv/insns/aes64es.h
new file: riscv/insns/aes64esm.h
deleted: riscv/insns/aesds.h
deleted: riscv/insns/aesdsm.h
deleted: riscv/insns/aeses.h
deleted: riscv/insns/aesesm.h
modified: riscv/processor.cc
modified: riscv/processor.h
modified: riscv/riscv.mk.in
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These instructions are RV32 only. Previously, they zero-extended
their 32-bit result to 64-bits, to match the Spike implementation detail
that the X registers are always 64-bits long.
This exposed a data dependant problem when the instruction results fed
into the add and sltu instructions. The lack of sign extension on the
sha512*, combined with the presence of sign extension on the add, meant
sltu would (as it is currently implemented) produce the wrong result.
There were two potential fixes:
1) Sign extend from 32-bits to XLEN the result of the SHA512 instructions.
2) Change the SLTU implementation to truncate RS1/RS2 to be XLEN bits
before it does the comparison.
This patch implements option 1, because I didn't want to mess with a
base ISA instruction. However, this leaves the implementation detail
open to cause problems for people in the future. Fixing this is outside
the scope of this commit.
On branch scalar-crypto-fix
Changes to be committed:
modified: riscv/insns/sha512sig0h.h
modified: riscv/insns/sha512sig0l.h
modified: riscv/insns/sha512sig1h.h
modified: riscv/insns/sha512sig1l.h
modified: riscv/insns/sha512sum0r.h
modified: riscv/insns/sha512sum1r.h
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