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AgeCommit message (Expand)AuthorFilesLines
2021-06-02Remove Duff's Device in main simulation loop (#721)Andrew Waterman3-58/+12
2021-06-02Accept Zba, Zbb, Zbc, Zbs ISA stringsAndrew Waterman46-45/+85
2021-06-02Fix ambiguous if/else warningAndrew Waterman1-1/+1
2021-06-02Fix CSR read-only check regression introduced in 463001198Andrew Waterman1-1/+5
2021-05-25Add alignment check for lr instruction (#713)sven3-3/+6
2021-05-20Don't raise virtual instruction exceptions writes to read-only registersAndrew Waterman1-2/+1
2021-05-17Implement satp/vsatp WARLness correctlyAndrew Waterman2-33/+36
2021-05-17Enforce hgatp WARLness in concordance with the specAndrew Waterman1-9/+15
2021-05-10Support RISC-V p-ext-proposal v0.9.2 (#637)ChunPing Chung334-1/+4228
2021-05-08in get_csr, use ret macro instead of return statementAndrew Waterman1-2/+2
2021-05-01Improve coding style of logging printfsAndrew Waterman4-21/+16
2021-05-01Fix compiler warning (#706)jmonesti1-2/+2
2021-04-27Implement JTAG BYPASS register. (#697)Tim Newsome2-11/+15
2021-04-13Display 32 bits (#693)emelcher3-11/+39
2021-04-05replace old compliance name with new arch-test name in spike target README (#...Allen Baum1-6/+6
2021-03-26Add missing require_rv64 for rv64-only insns. (#684)marcfedorow6-0/+6
2021-03-25Merge pull request #683 from huaixv/masterAndrew Waterman0-0/+0
2021-03-25Fix statx configure checkAndrew Waterman2-3/+3
2021-03-26Fix `stx_ino` member name in commit b65ead8huaixv2-3/+3
2021-03-25Fix xperm.[bhn] on RV32Andrew Waterman3-3/+3
2021-03-25Fix Ubuntu 16.04 buildAndrew Waterman3-0/+22
2021-03-25Merge pull request #681 from huaixv/masterAndrew Waterman4-0/+166
2021-03-25Add `statx` syscallhuaixv4-0/+166
2021-03-24Merge pull request #680 from scottj97/fix-vs-interruptsAndrew Waterman1-1/+1
2021-03-24HS-level interrupts should always be enabled when in VS-modeScott Johnson1-1/+1
2021-03-10Fix and refactor RV32-only and RV64-only instruction handlingAndrew Waterman2-16/+14
2021-03-10Stylistic changesAndrew Waterman2-11/+10
2021-03-08When disabling hypervisor via misa, clear hypervisor stateScott Johnson1-2/+8
2021-03-08Extract hypervisor_exceptions variableScott Johnson1-7/+8
2021-03-08Merge pull request #649 from ben-marshall/scalar-crypto-fixAndrew Waterman23-262/+296
2021-03-07Forbid `csrw vsstatus` from modifying the UXL field (#671)Scott Johnson1-0/+1
2021-03-05Fix vsstatus.FS misbehavior (#661)Scott Johnson2-35/+10
2021-03-05Fix bug where hstatus.SPVP was being changed when it should not be (#667)Scott Johnson1-1/+2
2021-03-05Don't make MPRV load/store virtual if MPV=1, MPP=3 (#666)jameshippisley1-1/+1
2021-03-05Fix hedeleg to match Privileged Spec requirements (#669)Scott Johnson1-0/+2
2021-03-04Fix bug where CSRW to vsstatus would not set SD correctly (#665)Scott Johnson1-1/+1
2021-03-02Hard-wire VSXL field in RV64 hstatus (#664)Scott Johnson1-0/+2
2021-03-02Fix AMO guest page fault as store guest fault (#663)francis40961-0/+3
2021-03-01Correct RV64 vsstatus.UXL field (#659)Scott Johnson1-0/+1
2021-02-25Merge pull request #655 from chihminchao/rvv-v0.10Andrew Waterman28-48/+64
2021-02-25Reindent to match style of surrounding codeScott Johnson1-2/+2
2021-02-25Update comment to match misa capabilitiesScott Johnson1-1/+1
2021-02-24rvv: update readmeChih-Min Chao1-1/+1
2021-02-24rvv: add vsetivliChih-Min Chao5-1/+9
2021-02-24rvv: totally remove edivChih-Min Chao2-4/+1
2021-02-24rvv: add vse1/vle1Chih-Min Chao22-28/+43
2021-02-23rvv: rename sqrt/reciprocal instructionsChih-Min Chao5-11/+11
2021-02-23rvv: disas: reserved sew >= 128Chih-Min Chao1-4/+0
2021-02-18scalar-crypto: Fix decoding of RV64 AES instructions.Ben Marshall17-238/+272
2021-02-18scalar-crypto: Fix RV32 sha512 instructions.Ben Marshall6-24/+24
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