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2019-11-11rvv: update version informationChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add 'V' ext check for each vector insnChih-Min Chao1-1/+1
'require_vector' should appear in front of each instruction and this trigger illegal exception when V extension isn't supported. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix reg checking for vmadc/vmsbcChih-Min Chao5-5/+0
remove unecessary checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao14-79/+51
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule to vslide instructionsChih-Min Chao6-10/+37
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for ldstChih-Min Chao17-8/+32
include 1. unit-stride 2. strided 3. indexed 4. fault-first Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for general fomratChih-Min Chao18-5/+38
for most instruction which are in single, single, single/scalar/immediate format Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for comparison instrucitonsChih-Min Chao11-11/+29
include: 1. integer comparison 2. float comparison Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for reductionChih-Min Chao1-5/+12
include 1. vredxxx 2. vwredxxx since reduction keep the accumulation result in pipeline and write 1 widen element back to dst register. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add register using check for wide and narrow insnChih-Min Chao19-51/+66
include 1. narrow shift 2. narrow clip 3. wide mac Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao2-5/+18
1. fix the ELAN check for vill 2. handle 'rs1 = x0' 3. make logic more readable Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix vsmul sign and variable typeChih-Min Chao2-25/+23
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix vssr/vssra rounding issueChih-Min Chao6-12/+19
use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix the rounding bit position for vnclip instructions.Albert Ou6-50/+34
1. The rounding increment should be derived from the shift amount, not SEW. 2. Use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Albert Ou <aou@eecs.berkeley.edu> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix INT_ROUNDING complianceAlbert Ou1-14/+10
* round-to-nearest-even: In the case that result[gb] = 0, the result should still be rounded up if result[gb-1] != 0 && result[gb-2:0] != 0 (the usual round-to-nearest behavior outside of the tiebreaker). * round-down: Since all uses of INT_ROUNDING() are immediately followed with a right shift by gb, clearing the lower bits is unnecessary. * round-to-odd: The LSB should be OR'd only if result[gb-1:0] != 0. Signed-off-by: Albert Ou <aou@eecs.berkeley.edu>
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao16-186/+41
tail zero feature has been removed after v0.8-draft Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix redsum/vmv for non-tail-zero caseChih-Min Chao3-28/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix vmv.x.s signed-ext issueChih-Min Chao2-23/+26
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-29rvv: fix floating-point exception for comparisonChih-Min Chao6-5/+6
don't use quiet api Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-29rvv: remove vmfordChih-Min Chao5-19/+0
has been removed in https://github.com/riscv/riscv-v-spec/pull/249 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-28Merge pull request #320 from zeldin/byteorderAndrew Waterman13-78/+136
Implement support for big-endian hosts
2019-10-28Whithhold BE ELF loading until BE target support is availableMarcus Comstedt1-9/+3
2019-10-28Implement support for big-endian hostsMarcus Comstedt13-78/+142
2019-10-24Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
Otherwise they are left uninitialized and causing bizarre reproducibility problems in my application.
2019-10-22Catch polymorphic exceptions by reference (#352)Luís Marques1-2/+2
2019-10-22Stop loading "past the end" of the vector. (#351)Nick Knight1-5/+5
2019-10-18Add user write permissions to installed filesAndrew Waterman1-2/+2
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman2-2/+10
It's very difficult to encounter this (need to manually place a device or memory at very high addresses), but it is technically a Spike bug.
2019-10-07Speed up compilation of disasm.cc, especially in clangAndrew Waterman3-3/+5
2019-10-07update changelogAndrew Waterman1-0/+3
2019-09-27Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
Mask calculation was not in consistency with debug spec. Watch debug spec. 5.2.7 match field overview and debug spec. B.9 fourth example. Mask should not cover LSB zero bit. Also there is a way to make it simplier: reg_t mask = ~(((~state.tdata2[i]) - 1) ^ ~state.tdata2[i]);
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion3-6/+37
* Extends the commit log feature with memory writes. This provides a little more information for debugging instruction traces, allowing you to maintain the state of memory as the trace is processed. The following sample trace output illustrates the formatting of the new memory writes. The first line is an instruction at location 0x80000094, containing the bytes (0x80830313) and commiting the value 0x80000898 to the register x6. The second line is an instruction which neither commits a register nor writes memory. The third line writes the value 0x0 to 0x80000890. 3 0x80000094 (0x80830313) x 6 0x80000898 3 0x80000098 (0x0062d663) 3 0x8000009c (0x00028023) mem 0x80000890 0x0 * Changes addressing feedback from review.
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion6-2/+34
* Adds --log-commits commandline option. Similar to histogram support, the commit logging feature must be enabled with a configure option: --enable-commitlog. However, unlike that feature, there was no way to turn off the logging with a commandline option once the functionality was built in. This (git) commit provides that abilty. * Changes addressing review feedback.
2019-09-05Fix formatting in READMEAndrew Waterman1-1/+1
Closes #328
2019-09-02Fix OSX buildAndrew Waterman3-2/+131
Closes #326
2019-08-28Merge pull request #315 from vexingcodes/mmio-pluginAndrew Waterman9-7/+225
Implement MMIO device plugins.
2019-08-23Fix c.fldsp/c.fsdsp disassembly bugAndrew Waterman1-2/+2
2019-08-23Remove statement with no effectAndrew Waterman1-1/+0
2019-07-22Implement MMIO device plugins.Aaron Jones9-7/+225
2019-07-19Set vtype.vill correctly; also reset it to trueAndrew Waterman1-3/+8
Resolves #313
2019-07-19Check presence of V extension when accessing vector CSRsAndrew Waterman1-0/+15
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman24-20/+37
2019-07-19VL and VTYPE aren't writable CSRsAndrew Waterman1-12/+0
2019-07-19Check for F extension in vfmv instructionsAndrew Waterman2-0/+2
2019-07-19Avoid relying on sizeof longAndrew Waterman3-5/+5
2019-07-19Link with libsoftfloat.a (but still build libsoftfloat.so)Andrew Waterman1-4/+4
2019-07-19vext.x.v -> vmv.x.s; unary operation encoding changesAndrew Waterman5-45/+40
https://github.com/riscv/riscv-v-spec/commit/83fc27897b7b1fbc68e2e9e94f2ee05766315bac https://github.com/riscv/riscv-v-spec/commit/fb40ef10f068827f3f0a926a83dd38ebcd470085
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome7-16/+60
* Don't corrupt s0 when abstract CSR write fails. * Support abstract FPR access then mstatus.FS=0 Discussion on the spec list leans towards this being a requirement. Certainly users want their debugger to be able to access all registers regardless of target state.
2019-07-12Merge pull request #309 from riscv/dretAndrew Waterman5-12/+15
Fix DRET in M-mode, and change how D-mode is represented
2019-07-12Remove old header from makefileAndrew Waterman1-1/+0
Resolves #308
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