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2019-12-06fesvr: add support for system bus accesskritik bhimani1-2/+42
2019-12-06fesvr: Add --enable-sodor configure optionAlbert Ou3-3/+26
2019-12-06Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna2-1/+3
* SFENCE.VMA requires S-mode * MSTATUS.SUM hardwired to 0 if no S-Mode
2019-11-27Initialize mtimeAndrew Waterman1-1/+1
Closes #363
2019-11-27Fix (benign) uninitialized variableAndrew Waterman1-1/+1
2019-11-24Initialize state.misa prior to calls to supports_extensionAndrew Waterman1-0/+2
Partially reverts 0162a6e72421b5cbec1905b4cae7bfab98afe83f Closes #361
2019-11-15add vaaddu/vasubu/vfncvt.rod.f.f.v to diassemblerAndrew Waterman1-2/+5
2019-11-15Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman2-44/+55
2019-11-13Merge pull request #356 from riscv/priv-flagAndrew Waterman13-31/+106
Add --priv command-line option to set which privilege modes are available
2019-11-12mstatus.FS only exists if (S || V || F)Andrew Waterman1-1/+5
2019-11-12Remove S-mode interrupts when S-mode not presentAndrew Waterman1-5/+12
2019-11-12Fix mode-transition logic when S-mode not presentAndrew Waterman1-1/+1
2019-11-12SRET requires S-modeAndrew Waterman1-0/+1
2019-11-12Remove S-mode CSRs when S-mode is not presentAndrew Waterman1-1/+2
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman11-13/+73
2019-11-12Factor out boilerplate strtolower functionAndrew Waterman1-3/+9
2019-11-12In parse_isa_string, populate max_isa rather than state.misaAndrew Waterman1-7/+3
reset will copy max_isa over to state.misa.
2019-11-12Merge pull request #355 from chihminchao/rvv-0.8-2019-11Andrew Waterman108-514/+442
rvv-0.8-2019-11
2019-11-11rvv: update version informationChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add 'V' ext check for each vector insnChih-Min Chao1-1/+1
'require_vector' should appear in front of each instruction and this trigger illegal exception when V extension isn't supported. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix reg checking for vmadc/vmsbcChih-Min Chao5-5/+0
remove unecessary checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao14-79/+51
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule to vslide instructionsChih-Min Chao6-10/+37
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for ldstChih-Min Chao17-8/+32
include 1. unit-stride 2. strided 3. indexed 4. fault-first Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for general fomratChih-Min Chao18-5/+38
for most instruction which are in single, single, single/scalar/immediate format Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for comparison instrucitonsChih-Min Chao11-11/+29
include: 1. integer comparison 2. float comparison Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking rule for reductionChih-Min Chao1-5/+12
include 1. vredxxx 2. vwredxxx since reduction keep the accumulation result in pipeline and write 1 widen element back to dst register. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add register using check for wide and narrow insnChih-Min Chao19-51/+66
include 1. narrow shift 2. narrow clip 3. wide mac Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao2-5/+18
1. fix the ELAN check for vill 2. handle 'rs1 = x0' 3. make logic more readable Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix vsmul sign and variable typeChih-Min Chao2-25/+23
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix vssr/vssra rounding issueChih-Min Chao6-12/+19
use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix the rounding bit position for vnclip instructions.Albert Ou6-50/+34
1. The rounding increment should be derived from the shift amount, not SEW. 2. Use 128bit to store temporary result to handle shift = 63 case in rv64 Signed-off-by: Albert Ou <aou@eecs.berkeley.edu> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix INT_ROUNDING complianceAlbert Ou1-14/+10
* round-to-nearest-even: In the case that result[gb] = 0, the result should still be rounded up if result[gb-1] != 0 && result[gb-2:0] != 0 (the usual round-to-nearest behavior outside of the tiebreaker). * round-down: Since all uses of INT_ROUNDING() are immediately followed with a right shift by gb, clearing the lower bits is unnecessary. * round-to-odd: The LSB should be OR'd only if result[gb-1:0] != 0. Signed-off-by: Albert Ou <aou@eecs.berkeley.edu>
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao16-186/+41
tail zero feature has been removed after v0.8-draft Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix redsum/vmv for non-tail-zero caseChih-Min Chao3-28/+27
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: fix vmv.x.s signed-ext issueChih-Min Chao2-23/+26
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-29rvv: fix floating-point exception for comparisonChih-Min Chao6-5/+6
don't use quiet api Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-29rvv: remove vmfordChih-Min Chao5-19/+0
has been removed in https://github.com/riscv/riscv-v-spec/pull/249 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-10-28Merge pull request #320 from zeldin/byteorderAndrew Waterman13-78/+136
Implement support for big-endian hosts
2019-10-28Whithhold BE ELF loading until BE target support is availableMarcus Comstedt1-9/+3
2019-10-28Implement support for big-endian hostsMarcus Comstedt13-78/+142
2019-10-24Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
Otherwise they are left uninitialized and causing bizarre reproducibility problems in my application.
2019-10-22Catch polymorphic exceptions by reference (#352)Luís Marques1-2/+2
2019-10-22Stop loading "past the end" of the vector. (#351)Nick Knight1-5/+5
2019-10-18Add user write permissions to installed filesAndrew Waterman1-2/+2
2019-10-16Enforce 2^56-bit physical address limitAndrew Waterman2-2/+10
It's very difficult to encounter this (need to manually place a device or memory at very high addresses), but it is technically a Spike bug.
2019-10-07Speed up compilation of disasm.cc, especially in clangAndrew Waterman3-3/+5
2019-10-07update changelogAndrew Waterman1-0/+3
2019-09-27Fixed match trigger MATCH_NAPOT case. (#335)fborisovskii1-1/+1
Mask calculation was not in consistency with debug spec. Watch debug spec. 5.2.7 match field overview and debug spec. B.9 fourth example. Mask should not cover LSB zero bit. Also there is a way to make it simplier: reg_t mask = ~(((~state.tdata2[i]) - 1) ^ ~state.tdata2[i]);
2019-09-18Extends the commit log feature with memory writes. (#324)dave-estes-syzexion3-6/+37
* Extends the commit log feature with memory writes. This provides a little more information for debugging instruction traces, allowing you to maintain the state of memory as the trace is processed. The following sample trace output illustrates the formatting of the new memory writes. The first line is an instruction at location 0x80000094, containing the bytes (0x80830313) and commiting the value 0x80000898 to the register x6. The second line is an instruction which neither commits a register nor writes memory. The third line writes the value 0x0 to 0x80000890. 3 0x80000094 (0x80830313) x 6 0x80000898 3 0x80000098 (0x0062d663) 3 0x8000009c (0x00028023) mem 0x80000890 0x0 * Changes addressing feedback from review.
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