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AgeCommit message (Expand)AuthorFilesLines
2011-06-19temporary undoing of renamingAndrew Waterman439-0/+20247
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman439-20316/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman5-19/+35
2011-06-11[xcc] fixed simulator build timeAndrew Waterman6-77/+354
2011-06-11[xcc] tlb now stores host addressesAndrew Waterman2-19/+19
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman9-137/+185
2011-06-11[xcc] fix configure scriptsAndrew Waterman2-6/+6
2011-06-11[xcc] instructions now set PC explicitlyAndrew Waterman15-18/+32
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman21-12322/+377
2011-06-05[sim] fix writeback after ipi clearingAndrew Waterman1-0/+1
2011-06-04[sim] add ability to clear IPIsAndrew Waterman1-0/+3
2011-05-31[sim] fault on failed addr translationsAndrew Waterman1-1/+21
2011-05-31[sim] minor sim cleanupAndrew Waterman2-18/+8
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman23-2178/+12423
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman10-57/+127
2011-05-23[sim,xcc] add rdcycle/rdtime/rdinstretAndrew Waterman5-6/+6
2011-05-19[sim] more fp<->int fixesAndrew Waterman4-4/+4
2011-05-19[sim] more fp conversion bugs fixedAndrew Waterman2-2/+2
2011-05-19[sim] change default hwvlYunsup Lee1-3/+3
2011-05-19[sim] vlen calc reflects the hardwareYunsup Lee2-14/+11
2011-05-18[sim] fixed fcvt rounding bugsAndrew Waterman8-8/+8
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee6-51/+69
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman7-39/+70
2011-05-16[sim,xcc] change cond. mov inst format, add implementationYunsup Lee4-0/+8
2011-05-15[opcodes,pk,sim,xcc] resolve a conflictYunsup Lee1-4/+19
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee76-202/+212
2011-05-13[sim] initial support for virtual memoryAndrew Waterman3-18/+131
2011-05-13[sim] stubs for perfctr instructionsAndrew Waterman3-0/+3
2011-05-13tweaked encoding of rdcycle & cousinsAndrew Waterman1-23/+38
2011-05-06[sim] fixed building sim without cache simulatorsAndrew Waterman1-1/+1
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman8-43/+187
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman2-3569/+559
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman22-12/+2642
2011-04-23[sim] fixed divw/remw crashing simulatorAndrew Waterman2-6/+2
2011-04-18[xcc,sim] rv64 'w' instruction semantics changedAndrew Waterman2-2/+2
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman4-4/+53
2011-04-16[sim] removed undefined behavior for non-canonical inputsAndrew Waterman13-13/+15
2011-04-16[sim] added "str" debug commandAndrew Waterman2-0/+18
2011-04-15[sim] fixed jalr immediate bugAndrew Waterman1-2/+2
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman13-7/+154
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman2-0/+10
2011-04-12[xcc,sim] fixed RM fieldAndrew Waterman1-2/+4
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman10-1/+187
2011-04-12[sim,pk] fixed minor pk bugs and trap codesAndrew Waterman2-4/+7
2011-04-11[sim] fixed FSR exception field bugAndrew Waterman1-1/+1
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman8-6/+507
2011-04-09[sim] add disable option for vectorYunsup Lee4-0/+26
2011-04-09[sim] set SR_EV for utsYunsup Lee1-0/+1
2011-04-09[sim] add vector traps to vector instructionsYunsup Lee44-1/+44
2011-04-09[sim] add vt stuffYunsup Lee47-3/+189
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