aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2020-08-31softfloat: add reciprocal apiChih-Min Chao3-0/+399
2020-08-27rf: remove bit extraction from processor.hChih-Min Chao3-9/+18
2020-08-27rvv: remove quad instructionsChih-Min Chao12-64/+0
2020-08-20Fix debug tests failing with impebreak enabled. (#530)Tim Newsome1-1/+1
2020-08-20Merge pull request #533 from chihminchao/rvv-fix-2020-08-20Andrew Waterman1-1/+2
2020-08-20rvv: fix vrgatherei16 overlap ruleChih-Min Chao1-1/+2
2020-08-12mcounteren does not exist if U-mode is not implementedAndrew Waterman1-1/+4
2020-08-11Merge pull request #527 from sobuch/optional-impebreakAndrew Waterman3-7/+15
2020-08-11Add option to dissable implicit ebreak in program bufferSamuel Obuch3-7/+15
2020-08-04Merge pull request #521 from chihminchao/op-hypvervisorAndrew Waterman3-51/+51
2020-08-04Merge pull request #520 from chihminchao/rvv-enhance-vstartAndrew Waterman24-39/+48
2020-08-03op: hyperviosr: fix exception code and nameChih-Min Chao3-6/+6
2020-08-03op: rearrange hypbervisor op/csr/causeChih-Min Chao1-46/+46
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao23-36/+45
2020-08-03op: rvv: fix pesudo code instructionsChih-Min Chao1-3/+3
2020-07-30Merge pull request #519 from chihminchao/rvv-pre-1.0Andrew Waterman64-282/+483
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao3-18/+0
2020-07-29rvv: remove veew/vemul stateChih-Min Chao3-32/+25
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao4-13/+51
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao25-23/+212
2020-07-29rvv: op: rearrange some instruction since generation order changeChih-Min Chao1-36/+36
2020-07-29rvv: op: fix amo namingChih-Min Chao39-148/+148
2020-07-29rvv: remove slenChih-Min Chao2-8/+5
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
2020-07-29rvv: disasm: fix missing vamoorei operandsChih-Min Chao1-1/+2
2020-07-28Merge pull request #517 from riscv/rvv-1.0-vtypeAndrew Waterman2-5/+4
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman2-5/+4
2020-07-21Remove deprecated decoding of xor x0,x0,x0Andrew Waterman1-1/+0
2020-07-16Fix legalize_privilege for extension H (#508)Abhinay Kayastha1-1/+1
2020-07-15commitlog: fix vmvnfr.v register information (#506)Chih-Min Chao1-4/+17
2020-07-13rvv: fix viota.m dst and src overlapping rule (#504)Chih-Min Chao1-5/+1
2020-07-09Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1Andrew Waterman35-146/+946
2020-07-09Add kernel command line option for spikeAnup Patel1-0/+18
2020-07-09Add bootargs command-line option to SpikeAnup Patel5-8/+25
2020-07-09Implement new instructions of hypervisor extensionAnup Patel16-0/+81
2020-07-09Implement hypervisor two-stage MMUAnup Patel2-51/+179
2020-07-09Implement hypervisor CSRs read/writeAnup Patel8-53/+502
2020-07-08rvv: vstart register needs only lg2(VLEN) bits (#501)Chih-Min Chao1-1/+1
2020-07-08Extend trap classes to pass more informationAnup Patel7-28/+60
2020-07-08Add hypervisor extension related CSR and instruction definesAnup Patel1-6/+81
2020-07-07Merge pull request #500 from abhinay-kayastha/GetCsrZeroPmpUdit Khanna1-0/+3
2020-07-06If n_pmp=0, then pmp is not implemented hence raise trapAbhinay Kayastha1-0/+3
2020-07-04Merge pull request #499 from chihminchao/commitlog-2020-07-02Andrew Waterman5-39/+142
2020-07-02commitlog: support csr accessChih-Min Chao2-2/+99
2020-07-02commitlog: simplify print_value pathChih-Min Chao1-26/+27
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao3-6/+12
2020-07-02rvv: make vmvfnr respect vstartChih-Min Chao1-5/+4
2020-06-25Merge pull request #494 from chihminchao/rvv-fix-2020-06-25Andrew Waterman2-4/+5
generated by cgit v1.1 at 2024-07-11 14:11:55 +0000