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2020-07-29rvv: op: fix amo namingChih-Min Chao39-148/+148
2020-07-29rvv: remove slenChih-Min Chao2-8/+5
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
2020-07-29rvv: disasm: fix missing vamoorei operandsChih-Min Chao1-1/+2
2020-07-28Merge pull request #517 from riscv/rvv-1.0-vtypeAndrew Waterman2-5/+4
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman2-5/+4
2020-07-21Remove deprecated decoding of xor x0,x0,x0Andrew Waterman1-1/+0
2020-07-16Fix legalize_privilege for extension H (#508)Abhinay Kayastha1-1/+1
2020-07-15commitlog: fix vmvnfr.v register information (#506)Chih-Min Chao1-4/+17
2020-07-13rvv: fix viota.m dst and src overlapping rule (#504)Chih-Min Chao1-5/+1
2020-07-09Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1Andrew Waterman35-146/+946
2020-07-09Add kernel command line option for spikeAnup Patel1-0/+18
2020-07-09Add bootargs command-line option to SpikeAnup Patel5-8/+25
2020-07-09Implement new instructions of hypervisor extensionAnup Patel16-0/+81
2020-07-09Implement hypervisor two-stage MMUAnup Patel2-51/+179
2020-07-09Implement hypervisor CSRs read/writeAnup Patel8-53/+502
2020-07-08rvv: vstart register needs only lg2(VLEN) bits (#501)Chih-Min Chao1-1/+1
2020-07-08Extend trap classes to pass more informationAnup Patel7-28/+60
2020-07-08Add hypervisor extension related CSR and instruction definesAnup Patel1-6/+81
2020-07-07Merge pull request #500 from abhinay-kayastha/GetCsrZeroPmpUdit Khanna1-0/+3
2020-07-06If n_pmp=0, then pmp is not implemented hence raise trapAbhinay Kayastha1-0/+3
2020-07-04Merge pull request #499 from chihminchao/commitlog-2020-07-02Andrew Waterman5-39/+142
2020-07-02commitlog: support csr accessChih-Min Chao2-2/+99
2020-07-02commitlog: simplify print_value pathChih-Min Chao1-26/+27
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao3-6/+12
2020-07-02rvv: make vmvfnr respect vstartChih-Min Chao1-5/+4
2020-06-25Merge pull request #494 from chihminchao/rvv-fix-2020-06-25Andrew Waterman2-4/+5
2020-06-25rvv: remove unecessary accessChih-Min Chao1-3/+0
2020-06-25rvv: fix viota.m overlapping ruleChih-Min Chao1-1/+5
2020-06-17Merge pull request #491 from chihminchao/rvv-fix-2020-06-18Andrew Waterman3-4/+4
2020-06-17rvv: make v[sl]1r respect vstartChih-Min Chao2-2/+2
2020-06-17rvv: commitlog: fix fractional lmul dumpChih-Min Chao1-2/+2
2020-06-16Merge pull request #490 from chihminchao/rvv-fix-2020-06-17Andrew Waterman3-1/+11
2020-06-16rvv: disasm: fix vwadd.wx operandChih-Min Chao1-1/+1
2020-06-16zfh: support register dump in interactive modeChih-Min Chao2-0/+10
2020-06-16Merge pull request #489 from chihminchao/extension-zfhAndrew Waterman40-1/+357
2020-06-16ext: handle diaseembler initialization from --extensionChih-Min Chao1-0/+4
2020-06-16zfh: implement all instructionsChih-Min Chao37-1/+207
2020-06-16zfh: disasm: add fp16 disasmChih-Min Chao1-0/+38
2020-06-16zfh: op: add scalar opcodeChih-Min Chao1-0/+108
2020-06-15remove the redundant code (#488)Dave Wen2-2/+1
2020-06-11Merge pull request #486 from chihminchao/rvv-fix-2020-06-10Andrew Waterman6-29/+85
2020-06-11rvv: fix index and amo overlapping ruleChih-Min Chao1-4/+23
2020-06-11rvv: add widen overlapping helper and related widen ruleChih-Min Chao1-8/+52
2020-06-11rvv: fix comparison and narrow overlapping ruleChih-Min Chao1-3/+6
2020-06-11rvv: fix some style and dead codeChih-Min Chao3-12/+2
2020-06-11rvv: disasm: fix vfncvt.f.f.wChih-Min Chao1-1/+1
2020-06-10build: fix quota string parameterChih-Min Chao1-1/+1
2020-06-10Merge pull request #485 from chihminchao/custom-extAndrew Waterman13-30/+91
2020-06-10ext: add simple sifive cflush extensionChih-Min Chao2-0/+42
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