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2018-08-23Add dummy custom debug registers, to test OpenOCD. (#233)Tim Newsome2-0/+18
2018-08-23Fix several disassembler bugsAndrew Waterman2-57/+89
h/t Shane Lardinois
2018-08-23Add --disable-dtb option to suppress writing the DTB to memoryAndrew Waterman3-2/+11
2018-08-22Make IRQ_COP read-only/undelegable unless coprocessor is presentAndrew Waterman1-1/+2
2018-08-21Instantiate disassembler after max_xlen is knownAndrew Waterman1-1/+5
This fixes RVC disassembly. It's done in a way that doesn't break 2cd60b277e909a5599ca48e4561cbfbc61460186
2018-08-17Don't increment instret immediately after it is written (#231)Andrew Waterman1-0/+6
This brings Spike into compliance with this clause in the spec: https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96
2018-08-10Fix 2 trigger corner cases. (#229)Tim Newsome2-6/+14
1. When hitting a trigger during a single step, dcsr.cause must reflect the trigger not the step. 2. Also check for triggers on accesses that require a slow path fetch.
2018-07-31Make sstatus.MXR readableAndrew Waterman1-1/+1
h/t @taoliug
2018-07-23Fix using the uninitialized disassemble object. (#220)SeungRyeol Lee1-1/+1
This fixes runtime crash when custom extension registers its disassembly.
2018-07-10Refactor and fix LR/SC implementation (#217)Andrew Waterman9-11/+34
- Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612) - Don't yield reservation on exceptions (it's no longer required).
2018-06-11Merge pull request #212 from riscv/hartselTim Newsome3-285/+303
Update debug_defines.h
2018-06-11Update debug_defines.hTim Newsome3-285/+303
Add support for hartselhi parsing, but other parts of the debug code still don't support more than 1024 harts.
2018-05-31Put simif_t declaration in its own file. (#209)Andy Wright7-16/+27
By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr.
2018-05-18Fix install of missed header. (#207)Prashanth Mundkur1-0/+1
2018-05-18Extract out device-tree generation and compilation into an exported api. (#197)Prashanth Mundkur4-142/+175
2018-05-04Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"Andrew Waterman2-0/+2
See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59
2018-05-03C.LWSP and C.LDSP with rd=0 are legal instructionsAndrew Waterman2-2/+0
This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982
2018-04-30Fix commit log for serializing instructionsAndrew Waterman1-1/+1
Resolves #199
2018-04-30Only break out of the simulator loop on WFI, not on CSR writesAndrew Waterman3-2/+9
Breaking out of the loop on WFI was intended to let other threads run when the current thread has no work to do. There's no advantage to doing so on CSR writes, and the unintentional change in thread interleaving broke some test programs that relied on short timer periods.
2018-04-29When no arguments are passed, print spike help, not fesvr helpAndrew Waterman1-3/+3
2018-04-04Allow querying the mmu configuration chosen during the build. (#191)Prashanth Mundkur1-0/+18
2018-04-04Revert "Fix for issue #183: No illegal instruction exception for c.sxxi ↵Andrew Waterman3-3/+3
instructions encoded with zero shift amount" This reverts commit be0555d585b332fd0496affe559c0a5a4e7e5644. See #190
2018-03-30Merge pull request #189 from pmundkur/pm-csr-name-apiPalmer Dabbelt2-0/+10
Add an api to get the name for a CSR.
2018-03-26Add an api to get the name for a CSR.Prashanth Mundkur2-0/+10
2018-03-21Implement Hauser misa.C misalignment proposal (#187)Andrew Waterman4-6/+12
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7 - Reads of xEPC[1] are masked when RVC is disabled - Writes to MISA are suppressed if they would cause a misaligned fetch - Misaligned PCs no longer need to be checked upon fetch
2018-03-21Fix the access exception during page-table walks to match the original ↵Prashanth Mundkur1-1/+9
access type, as specified in the manual. (#185)
2018-03-19Fix spike-dasm. (#184)Tim Newsome1-1/+2
It had been broken by 90bafe660b323250338fd564bb9ab4316576d59b.
2018-03-19Merge pull request #182 from riscv/reset_bitsTim Newsome5-1/+33
Implement debug havereset bits
2018-03-16Implement debug havereset bitsTim Newsome5-1/+33
2018-03-16Merge branch 'deepsrc-b_fix_issue183'Andrew Waterman19-59/+117
2018-03-16Fix for issue #183: No illegal instruction exception for c.sxxi instructions ↵Shubhodeep Roy Choudhury3-3/+3
encoded with zero shift amount
2018-03-14Fix a bug caused by moving misa into state_t. (#180)Prashanth Mundkur2-3/+4
* Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization. Make state:reset() preserve misa. * Set state.misa to max_isa on reset(). * Idiomatic fix for earlier commit.
2018-03-13Move processor.isa to state.misa, since it really belongs there.Prashanth Mundkur2-10/+10
2018-03-09Fix single stepping csrrw instructions (#178)Tim Newsome1-8/+7
This code is still a bit voodoo to me, but now we pass all the tests again. (Stepping was broken by 4299874ad4b07ef457776513a64e5b2397a6a75e.)
2018-03-07Merge pull request #177 from riscv/debug_authTim Newsome6-13/+59
Add debug module authentication.
2018-03-06Narrow the interface used by the processors and memory to the top-level ↵Prashanth Mundkur8-17/+28
simulator/htif. This allows the implementation of an alternative top-level simulator class.
2018-03-06Fix install of a missed header from debug_rom.Prashanth Mundkur4-5/+5
The installed header files from the riscv subproject were incomplete, since processor.h includes debug_rom_defines.h, and the latter was not installed. Fix by moving it into riscv/, add it to the riscv subproject header list, which ensures it will get installed. While here, also add a missed dependency of debug_rom on riscv/encoding.h to debug_rom/Makefile.
2018-03-06Fix a missed header file in the softfloat include install.Prashanth Mundkur2-0/+1
2018-03-03Implement clearing-misa.C-while-PC-is-misaligned proposalAndrew Waterman9-3/+15
See https://github.com/riscv/riscv-isa-manual/pull/139 Not adopted yet, but I'm putting the implementation here for reference.
2018-03-03Enforce 2-byte alignment of mepc/sepc/dpcAndrew Waterman1-3/+3
2018-03-01Merge pull request #173 from riscv/no_progbuf3Tim Newsome2-35/+98
Add support for abstract debug access to CSRs and FPRs
2018-02-27Add debug module authentication.Tim Newsome6-13/+59
Off by default, enabled with --debug-auth. The protocol is very simple (definitely not secure) to allow debuggers to test their authentication feature. To authenticate a debugger must: 1. Read authdata 2. Write to authdata the value that it just read, plus 1
2018-02-21Don't allow 32-bit instructions to take up multiple slots in I$Andrew Waterman2-17/+4
I$ indices now maintain a 1:N relationship with PCs. This is somewhat faster and also simpler.
2018-02-19Merge pull request #171 from riscv/sysbusbitsTim Newsome6-91/+299
Add support for debug bus mastering
2018-02-19Passes smoke tests with --progsize=0Tim Newsome1-15/+82
2018-02-19WIP. Doesn't work.Tim Newsome2-40/+36
2018-02-13Implement cycleh/instreth CSRs for RV32 (#172)Andrew Waterman1-0/+5
2018-02-01Add --debug-sba optionTim Newsome5-52/+50
This lets the user control whether the system bus access implements bus mastering.
2018-01-29Update debug_definesTim Newsome3-53/+53
2018-01-18Support debug system bus access.Tim Newsome5-20/+230
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