index
:
rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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2018-08-23
Add dummy custom debug registers, to test OpenOCD. (#233)
Tim Newsome
2
-0
/
+18
2018-08-23
Fix several disassembler bugs
Andrew Waterman
2
-57
/
+89
2018-08-23
Add --disable-dtb option to suppress writing the DTB to memory
Andrew Waterman
3
-2
/
+11
2018-08-22
Make IRQ_COP read-only/undelegable unless coprocessor is present
Andrew Waterman
1
-1
/
+2
2018-08-21
Instantiate disassembler after max_xlen is known
Andrew Waterman
1
-1
/
+5
2018-08-17
Don't increment instret immediately after it is written (#231)
Andrew Waterman
1
-0
/
+6
2018-08-10
Fix 2 trigger corner cases. (#229)
Tim Newsome
2
-6
/
+14
2018-07-31
Make sstatus.MXR readable
Andrew Waterman
1
-1
/
+1
2018-07-23
Fix using the uninitialized disassemble object. (#220)
SeungRyeol Lee
1
-1
/
+1
2018-07-10
Refactor and fix LR/SC implementation (#217)
Andrew Waterman
9
-11
/
+34
2018-06-11
Merge pull request #212 from riscv/hartsel
Tim Newsome
3
-285
/
+303
2018-06-11
Update debug_defines.h
Tim Newsome
3
-285
/
+303
2018-05-31
Put simif_t declaration in its own file. (#209)
Andy Wright
7
-16
/
+27
2018-05-18
Fix install of missed header. (#207)
Prashanth Mundkur
1
-0
/
+1
2018-05-18
Extract out device-tree generation and compilation into an exported api. (#197)
Prashanth Mundkur
4
-142
/
+175
2018-05-04
Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"
Andrew Waterman
2
-0
/
+2
2018-05-03
C.LWSP and C.LDSP with rd=0 are legal instructions
Andrew Waterman
2
-2
/
+0
2018-04-30
Fix commit log for serializing instructions
Andrew Waterman
1
-1
/
+1
2018-04-30
Only break out of the simulator loop on WFI, not on CSR writes
Andrew Waterman
3
-2
/
+9
2018-04-29
When no arguments are passed, print spike help, not fesvr help
Andrew Waterman
1
-3
/
+3
2018-04-04
Allow querying the mmu configuration chosen during the build. (#191)
Prashanth Mundkur
1
-0
/
+18
2018-04-04
Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instr...
Andrew Waterman
3
-3
/
+3
2018-03-30
Merge pull request #189 from pmundkur/pm-csr-name-api
Palmer Dabbelt
2
-0
/
+10
2018-03-26
Add an api to get the name for a CSR.
Prashanth Mundkur
2
-0
/
+10
2018-03-21
Implement Hauser misa.C misalignment proposal (#187)
Andrew Waterman
4
-6
/
+12
2018-03-21
Fix the access exception during page-table walks to match the original access...
Prashanth Mundkur
1
-1
/
+9
2018-03-19
Fix spike-dasm. (#184)
Tim Newsome
1
-1
/
+2
2018-03-19
Merge pull request #182 from riscv/reset_bits
Tim Newsome
5
-1
/
+33
2018-03-16
Implement debug havereset bits
Tim Newsome
5
-1
/
+33
2018-03-16
Merge branch 'deepsrc-b_fix_issue183'
Andrew Waterman
19
-59
/
+117
2018-03-16
Fix for issue #183: No illegal instruction exception for c.sxxi instructions ...
Shubhodeep Roy Choudhury
3
-3
/
+3
2018-03-14
Fix a bug caused by moving misa into state_t. (#180)
Prashanth Mundkur
2
-3
/
+4
2018-03-13
Move processor.isa to state.misa, since it really belongs there.
Prashanth Mundkur
2
-10
/
+10
2018-03-09
Fix single stepping csrrw instructions (#178)
Tim Newsome
1
-8
/
+7
2018-03-07
Merge pull request #177 from riscv/debug_auth
Tim Newsome
6
-13
/
+59
2018-03-06
Narrow the interface used by the processors and memory to the top-level simul...
Prashanth Mundkur
8
-17
/
+28
2018-03-06
Fix install of a missed header from debug_rom.
Prashanth Mundkur
4
-5
/
+5
2018-03-06
Fix a missed header file in the softfloat include install.
Prashanth Mundkur
2
-0
/
+1
2018-03-03
Implement clearing-misa.C-while-PC-is-misaligned proposal
Andrew Waterman
9
-3
/
+15
2018-03-03
Enforce 2-byte alignment of mepc/sepc/dpc
Andrew Waterman
1
-3
/
+3
2018-03-01
Merge pull request #173 from riscv/no_progbuf3
Tim Newsome
2
-35
/
+98
2018-02-27
Add debug module authentication.
Tim Newsome
6
-13
/
+59
2018-02-21
Don't allow 32-bit instructions to take up multiple slots in I$
Andrew Waterman
2
-17
/
+4
2018-02-19
Merge pull request #171 from riscv/sysbusbits
Tim Newsome
6
-91
/
+299
2018-02-19
Passes smoke tests with --progsize=0
Tim Newsome
1
-15
/
+82
2018-02-19
WIP. Doesn't work.
Tim Newsome
2
-40
/
+36
2018-02-13
Implement cycleh/instreth CSRs for RV32 (#172)
Andrew Waterman
1
-0
/
+5
2018-02-01
Add --debug-sba option
Tim Newsome
5
-52
/
+50
2018-01-29
Update debug_defines
Tim Newsome
3
-53
/
+53
2018-01-18
Support debug system bus access.
Tim Newsome
5
-20
/
+230
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