rocket-tools/riscv-gnu-toolchain/spike.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-04-17	debug: Use more unique debug ROM names	Megan Wachs	3	-16/+32
2017-04-17	debug: Use a more practical debug ROM	Megan Wachs	4	-161/+83
2017-04-17	debug: Move things around, but addresses now conflict with ROM.	Megan Wachs	5	-119/+93
2017-04-17	debug: consider COMMAND.transfer bit, and implment HARTINFO	Megan Wachs	1	-9/+20
2017-04-17	debug: Compiles again with new debug_defines.h file, but not tested.	Megan Wachs	2	-12/+4
2017-04-17	debug: bump the debug_defines to match spec	Megan Wachs	1	-149/+61
2017-04-17	Merge remote-tracking branch 'origin/priv-1.10' into HEAD	Megan Wachs	87	-340/+1065
2017-04-10	Implement new FP encoding	Andrew Waterman	57	-70/+93
2017-04-07	Implement vectored interrupt proposal	Andrew Waterman	1	-3/+5
2017-04-05	Add --enable-misaligned option for misaligned ld/st support	Andrew Waterman	4	-4/+50
2017-03-31	update encoding.h to get PMP updates	Yunsup Lee	1	-5/+6
2017-03-31	Update LICENSE copyright date	Andrew Waterman	1	-2/+2
2017-03-30	fdt: move interrupt controller into its own node	Wesley W. Terpstra	1	-4/+7
2017-03-27	Set badaddr=0 on illegal instruction traps	Andrew Waterman	4	-7/+7
2017-03-27	On EBREAK, set badaddr to pc	Andrew Waterman	3	-3/+3
2017-03-27	Separate page faults from physical memory access exceptions	Andrew Waterman	4	-13/+25
2017-03-24	Default to 2 GiB of memory	Andrew Waterman	1	-1/+1
2017-03-23	Require little-endian host	Andrew Waterman	2	-0/+14
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	8	-55/+96
2017-03-21	sim: declare cores as interrupt-controllers for clint	Wesley W. Terpstra	1	-0/+2
2017-03-21	bootrom: set a0 to hartid and a1 to dtb before boot	Wesley W. Terpstra	1	-7/+7
2017-03-21	configstring: rename variables to dts	Wesley W. Terpstra	3	-12/+12
2017-03-21	riscv: remove dependency on num_cores	Wesley W. Terpstra	3	-5/+1
2017-03-21	bootrom: include compiled dtb	Wesley W. Terpstra	1	-1/+87
2017-03-21	sim: create DTS instead of config string	Wesley W. Terpstra	1	-26/+45
2017-03-21	sim: define emulated CPU clock rate to be 1GHz	Wesley W. Terpstra	1	-0/+1
2017-03-21	autoconf: put location of 'dtc' into config.h	Wesley W. Terpstra	4	-0/+52
2017-03-21	spec bump	Palmer Dabbelt	4	-442/+565
2017-03-20	PUM -> SUM; expose MXR to S-mode	Andrew Waterman	3	-8/+9
2017-03-16	Simplify interrupt-stack discipline	Andrew Waterman	4	-4/+44
2017-03-13	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	Andrew Waterman	5	-4/+12
2017-03-07	Don't overload illegal instruction trap in interactive code	Andrew Waterman	1	-8/+10
2017-02-26	Sv57 and Sv64 are not spec'd yet	Andrew Waterman	2	-15/+11
2017-02-25	New counter enable scheme	Andrew Waterman	3	-31/+22
2017-02-25	Update bits to latest spec.	Tim Newsome	3	-593/+590
2017-02-23	Implement halt request.	Tim Newsome	3	-34/+5
2017-02-21	Improve debug performance.	Tim Newsome	4	-60/+76
2017-02-21	Don't waste time spinning in place in debug mode	Tim Newsome	1	-4/+7
2017-02-20	serialize simulator on wfi	Andrew Waterman	3	-4/+5
2017-02-20	Take M-mode interrupts over S-mode interrupts	Andrew Waterman	1	-1/+2
2017-02-20	permit MMIO loads to MSIP bit	Andrew Waterman	1	-7/+18
2017-02-18	Make HW setting of PTE A/D bits optional (by configure arg)	Andrew Waterman	4	-2/+45
2017-02-18	Spike uarch needs TLB flush after SPTBR write	Andrew Waterman	2	-1/+1
2017-02-17	Compress log output of jump-to-self loops.	Tim Newsome	1	-2/+16
2017-02-16	Remove noisy debugs.	Tim Newsome	1	-5/+0
2017-02-15	Set cmderr when data is accessed while busy.	Tim Newsome	1	-0/+8
2017-02-15	Implement autoexec. DMI op 2 is just write now.	Tim Newsome	3	-10/+44
2017-02-15	Implement resume (untested).	Tim Newsome	4	-31/+63
2017-02-15	sfence.vm -> sfence.vma	Andrew Waterman	3	-4/+4
2017-02-13	Implement program buffer preexec/postexec.	Tim Newsome	3	-44/+802