Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2023-02-05 | Make clint tolerant of discontiguous hart IDsplic-clint-endian | Andrew Waterman | 3 | -19/+26 | |
2023-02-05 | Fix CLINT on big-endian machines | Andrew Waterman | 1 | -23/+55 | |
This will also make it easier to support discontiguous hart IDs. | |||||
2023-02-04 | Fix PLIC on big-endian hosts | Andrew Waterman | 1 | -0/+2 | |
2023-02-04 | Correctly instantiate PLIC contexts for mixed-hart targets | Andrew Waterman | 3 | -11/+20 | |
This commit started as an attempt to make the PLIC tolerant of discontiguous hart IDs, but it turns out it was already most of the way there: PLIC contexts can still be dense even if the hart IDs are not. Nevertheless, I wanted to avoid passing the procs vector directly to the plic_t constructor. In removing it, I realized I could also get rid of the smode parameter by querying whether each hart has S-mode. This is also more correct; previously, we were instantiating the PLIC as though all harts had S-mode, regardless of whether they actually did. | |||||
2023-02-04 | Simplify plic_context_t initialization | Andrew Waterman | 1 | -9/+2 | |
2023-02-04 | Remove unused plic_context_t::num field | Andrew Waterman | 2 | -2/+0 | |
2023-02-04 | Remove unused plic_t::procs field | Andrew Waterman | 2 | -2/+1 | |
2023-02-04 | Make debug module tolerant of discontiguous hart IDs | Andrew Waterman | 2 | -48/+28 | |
The general strategy is to avoid iterating over the ID space. | |||||
2023-02-04 | Add sim_t::get_harts accessor | Andrew Waterman | 5 | -23/+29 | |
2023-02-03 | Improve input validation for --hartids flag | Andrew Waterman | 1 | -0/+18 | |
Disallow negative hartids, repeated hartids, and empty lists. | |||||
2023-02-02 | Merge pull request #1242 from riscv-software-src/publichtif | Andrew Waterman | 1 | -3/+3 | |
Make htif->get_to/fromhost_addr methods public | |||||
2023-02-02 | Make htif->get_to/fromhost_addr methods public | Jerry Zhao | 1 | -3/+3 | |
2023-01-31 | Merge pull request #1241 from riscv-software-src/zicond | Andrew Waterman | 6 | -2/+93 | |
Implement Zicond (conditional integer operations) | |||||
2023-01-31 | Zicond: implement Zicond (conditional integer operations) | Philipp Tomsich | 5 | -0/+12 | |
This implements the Zicond (conditional integer operations) extension, as of version 1.0-draft-20230120. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf for the proposed specification and usage details. | |||||
2023-01-31 | Update encoding.h for Zicond opcodes | Andrew Waterman | 1 | -2/+81 | |
Note this encoding.h's history is unusual because riscv-opcodes master is currently incompatible with Spike. See the PR that contains its commit hash (https://github.com/riscv/riscv-opcodes/pull/157) and discussion at https://github.com/riscv-software-src/riscv-isa-sim/pull/1234#discussion_r1092243338 | |||||
2023-01-30 | Merge pull request #1220 from YenHaoChen/pr-icount | Scott Johnson | 6 | -10/+130 | |
Add icount trigger | |||||
2023-01-30 | triggers: optimize icount_t::icount_check_needed() | YenHaoChen | 1 | -1/+1 | |
2023-01-30 | triggers: update README.md: add icount trigger | YenHaoChen | 1 | -1/+1 | |
2023-01-30 | triggers: add detect_icount_match() | YenHaoChen | 3 | -6/+65 | |
2023-01-30 | triggers: force to slow path with icount triggers | YenHaoChen | 4 | -2/+9 | |
2023-01-30 | triggers: add icount_t and update tinfo | YenHaoChen | 2 | -0/+52 | |
2023-01-30 | triggers: if match triggers with both breakpoint exception and entering ↵ | YenHaoChen | 1 | -6/+8 | |
D-mode, then enter D-mode and ignore breakpoint exception | |||||
2023-01-30 | triggers: refactor: use CSR_TDATA1_TYPE_MCONTROL6 instead of number 6 | YenHaoChen | 1 | -1/+1 | |
2023-01-27 | Merge pull request #1240 from adurbin-rivos/svadu | Andrew Waterman | 11 | -15/+17 | |
Add support for Svadu Extension | |||||
2023-01-27 | Remove dirty_enabled from cfg_t | Aaron Durbin | 5 | -8/+0 | |
The addition of Svadu support and removal of --mmu-dirty command line flag results in the dirty_enabled configuration state no longer being used. Remove the remnants of this state. | |||||
2023-01-27 | Remove --mmu-dirty command line flag | Aaron Durbin | 1 | -2/+0 | |
With the addition of Svadu support, the --mmu-dirty flag no longer controls behavior of A/D updates to PTEs. Remove the flag. | |||||
2023-01-27 | Use Svadu control bits to drive A/D updates | Aaron Durbin | 1 | -2/+4 | |
The Svadu (https://github.com/riscv/riscv-svadu) extension updates the A/D bits of PTEs: 1. In S/HS mode when menvcfg.hade=1 2. In G-stage page tables when menvcfg.hade=1 3. In VS mode when henvcfg.hade=1 To enable this behavior the 'svadu' ISA string is needed. This newly added behavior supplants the --mmu-dirty flag. However, that flag is not yet removed. | |||||
2023-01-27 | Enable Svadu control bits in menvcfg and henvcfg | Aaron Durbin | 2 | -1/+4 | |
Add in the support for the HADE fields in menvcfg and henvcfg based off of the svadu ISA string. This only allows for the writable HADE bits being exposed when the svadu ISA string is employed. No other behavior is implemented. | |||||
2023-01-27 | Add Svadu CSR bit definitions | Aaron Durbin | 1 | -2/+6 | |
The Svadu extension adds a HADE field (bit 61) to both menvcfg and henvcfg. Add the definitions so they can be utilized. | |||||
2023-01-27 | Add Svadu Extension Parsing to ISA Parser | Aaron Durbin | 2 | -0/+3 | |
Make the ISA parser understand the Svadu extension. | |||||
2023-01-20 | Merge pull request #1233 from riscv-software-src/pmp64 | Andrew Waterman | 3 | -18/+9 | |
Support all 64 PMP regions | |||||
2023-01-19 | Improve PMP number/granularity error messages | Andrew Waterman | 1 | -3/+4 | |
2023-01-19 | Perform pmpregions input validation in only one place | Andrew Waterman | 1 | -14/+4 | |
No reason to check it both in sim_t::sim_t and in processor_t::set_pmp_num. | |||||
2023-01-19 | Support all 64 PMP registers | Andrew Waterman | 1 | -1/+1 | |
2023-01-19 | Merge pull request #1219 from riscv-software-src/ntriggers | Andrew Waterman | 7 | -14/+26 | |
Add --triggers=n to control the number of supported triggers | |||||
2023-01-18 | Add --triggers flag to select number of triggers | Jerry Zhao | 1 | -0/+2 | |
2023-01-18 | Instantiate tdata/tinfo as const csrs when trigger_count == 0 | Jerry Zhao | 3 | -8/+12 | |
2023-01-18 | Add trigger_count field to cfg_t | Jerry Zhao | 5 | -6/+12 | |
2023-01-17 | Merge pull request #1232 from riscv-software-src/jerryz123-patch-1 | Andrew Waterman | 1 | -0/+3 | |
Add htif_t tohost/fromhost accessors | |||||
2023-01-17 | Add htif_t tohost/fromhost accessors | Jerry Zhao | 1 | -0/+3 | |
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu> | |||||
2023-01-16 | Merge pull request #1230 from gr816ox/patch-2 | Andrew Waterman | 1 | -0/+6 | |
Add more hint when searched path is wrong | |||||
2023-01-16 | Add more hint when searched path is wrong | gr816ox | 1 | -0/+6 | |
Delete the old branch and pull a new one, because of a wrong force push. Git is not as easy as I think. Signed-off-by: gr816ox <50945677+gr816ox@users.noreply.github.com> | |||||
2023-01-14 | Merge pull request #1228 from riscv-software-src/ext-limit | Andrew Waterman | 3 | -29/+31 | |
Lift artificial limit of 191 extensions; simplify isa_parser_t::extension_enabled | |||||
2023-01-13 | Simplify isa_parser_t::extension_enabled | Andrew Waterman | 1 | -4/+1 | |
Now that we guarantee that max_isa and extension_table are synchronized, we only need to check the latter. | |||||
2023-01-13 | Keep max_isa and extension_table in sync in exactly one place | Andrew Waterman | 1 | -22/+18 | |
This fixes a bug where --isa=rv64imafdc would fail to set extension_table['F'] because of the ad hoc manner in which we were synchronizing max_isa and extension_table. | |||||
2023-01-13 | Use more appropriate data structure for extension_table | Andrew Waterman | 2 | -3/+2 | |
We know its size at compile time. | |||||
2023-01-13 | Lift artificial limit of 191 extensions | Andrew Waterman | 3 | -1/+11 | |
Add new accessors that accept the isa_extension_t enum. Retain the original ones that accept unsigned char to avoid churn. | |||||
2023-01-13 | Merge pull request #1214 from YenHaoChen/pr-legalize-timing | Scott Johnson | 2 | -16/+22 | |
Add legalize_timing() for tdata1.timing | |||||
2023-01-13 | triggers: refactor: use static and remove const for legalize_action() | YenHaoChen | 2 | -2/+2 | |
Since this method does not use 'this', we turn this method into static. | |||||
2023-01-13 | triggers: refactor: use static and remove const for legalize_match() | YenHaoChen | 2 | -2/+2 | |
Since this method no longer use 'this', we turn this method into static. |