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2023-01-13triggers: refactor: remove legalization_action()'s dependency on dmodeYenHaoChen2-7/+8
avoid breaking functionality by reordering statements in tdata1.write()
2023-01-13triggers: legalize timing=1(after) for load data triggerYenHaoChen2-4/+7
As recommended in the debug spec table "Suggested Trigger Timings", to avoid the footgun of replaying a load (which may have side effects) when the breakpoint trap handler returns. reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1208#issuecomment-1373035906 ----------------------------------------------------------------------- The legalize_timing() depends on select, execution, load, and store, which are updated in the same function tdata1_write(). As a result, reordering statements in the tdata1_write() may break the functionality. Passing those variables as parameters to legalize_timing() does not solve the problem. Thus, we give the original write value and the masks of the variables to the legalize_timing(). This makes the legalization function independent of the updating variables and resolves the issue. reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1214
2023-01-12Merge pull request #1225 from riscv-software-src/no-threadsAndrew Waterman2-31/+14
Run Spike and HTIF in a single thread, rather than two
2023-01-12Merge pull request #1224 from riscv-software-src/uart-poll-less-oftenAndrew Waterman2-1/+12
For NS16550 UART, poll stdin less often
2023-01-12triggers: refactor: remove an outdated commentYenHaoChen1-1/+0
2023-01-12triggers: refactor: add mcontrol_common_t::legalize_timing() functionYenHaoChen2-6/+9
2023-01-11Run Spike and HTIF in a single thread, rather than twoAndrew Waterman2-31/+14
The two-thread approach was originally motivated by making Spike look as similar as possible to other HTIF targets. But we can get the same semantics without threading by running the simulator inside of the HTIF host's idle loop instead of performing a context switch. This was motivated by speeding up the simulator on Mac OS (it's worth around 20% because using pthread condition variables to force strict alternation is very slow). But I think it also simplifies the control flow enough to justify it on that basis, too.
2023-01-11Merge pull request #1212 from riscv-software-src/debug_smokeAndrew Waterman4-11/+84
Automatically test that external debug still works.
2023-01-11For NS16550 UART, poll stdin less oftenAndrew Waterman2-1/+12
On my Mac Mini, calling `poll()` on stdin takes around 10 us, and we are invoking it every 20 us or so. Reduce the frequency of polling by 16x when not actively receiving data, thereby reducing the fraction of time spent in `poll()` to a trivial amount.
2023-01-11Automatically test that external debug still works.Tim Newsome1-0/+64
2023-01-11Use nproc or hw.ncpu instead of -j4 to build spike.Tim Newsome1-1/+1
2023-01-11Refactor build-spike out of test-spike.Tim Newsome3-11/+20
2023-01-11Merge pull request #1223 from riscv-software-src/readmeAndrew Waterman1-1/+2
Fix supported debug version, use extension names
2023-01-11Fix supported debug version, use extension namesTim Newsome1-1/+2
Addresses #1221
2023-01-10Merge branch 'aap-sc-aap-sc/mem_cfg_corner_cases'Andrew Waterman4-16/+53
2023-01-10improve merge_mem_regions to handle memory region covering the whole 64-bit ↵Parshintsev Anatoly1-0/+24
address space
2023-01-10change mem_cfg_t to accept cases when (base + size) is at 64-bit address ↵Parshintsev Anatoly1-1/+5
space border
2023-01-09simplify check_mem_overlap by utilizing get_inclusive_end of mem_cfg_tParshintsev Anatoly1-4/+1
2023-01-09simplify merge_mem_regions by utilizing get_inclusive_end() of mem_cfg_tParshintsev Anatoly1-3/+3
this is to properly handle potential 64-bit overflow in (base + size) expression
2023-01-09get_inclusive_end implementation for mem_cfg_tParshintsev Anatoly2-3/+6
The method can simplify proper processing of sitiations when (base + size) overflows 64-bit interger.
2023-01-09implement get_size() getter for mem_cfg_t objectParshintsev Anatoly3-8/+13
NFT. We also mark `base` and `size` fields as private.
2023-01-09implement get_base() getter for mem_cfg_t objectParshintsev Anatoly3-11/+15
NFC. The intention is for `base` and `size` fields of mem_cfg_t to be private members. This is the fist part of this commit.
2023-01-05Merge pull request #1211 from riscv-software-src/speed-up-slow-pathAndrew Waterman1-2/+3
Only update histogram when histogramming
2023-01-05Remove vestigial UNUSED annotationAndrew Waterman1-1/+1
It dates back to when this code was ifdef'd.
2023-01-05Only update histogram when histogrammingAndrew Waterman1-1/+2
This is worth a 1.4x speedup on the slow path (when not histogramming).
2023-01-04Merge pull request #1210 from riscv-software-src/dynamic-dirty-enableAndrew Waterman9-67/+46
Control mmu-dirtying via command line
2023-01-04Remove --enable-dirty compile optionJerry Zhao3-24/+0
2023-01-04Respect --mmu-dirty flag instead of --enable-dirtyJerry Zhao2-24/+19
2023-01-04Add --mmu-dirty runtime flagJerry Zhao1-0/+2
2023-01-04Add cfg_t field to enable PTE dirtyingJerry Zhao4-0/+6
2023-01-04Untabify ci-tests/testlib.cJerry Zhao1-19/+19
2023-01-04Merge pull request #1209 from riscv-software-src/debugfixJerry Zhao2-5/+9
Fix debug-mode regression introduced by 20e7f53
2023-01-04Merge pull request #1207 from YenHaoChen/pr-trap-trigger-commonScott Johnson2-33/+34
triggers: refactor: add trap_common_t
2023-01-03Fix debug-mode regression introduced by 20e7f53Jerry Zhao2-5/+9
- Debug mode should break the processor out of wfi - wfi in debug mode should execute as a nop
2023-01-03Merge pull request #1206 from riscv-software-src/always_misalignedAndrew Waterman12-53/+42
Control whether misaligned accesses are supported via command line
2023-01-04triggers: refactor: move mode_match() and textra_match() to private for ↵YenHaoChen1-2/+2
protected
2023-01-04triggers: refactor: create trigger_t::common_match()YenHaoChen2-3/+7
2023-01-04triggers: refactor: move textra_match() to protected from publicYenHaoChen1-1/+1
2023-01-04triggers: refactor: move textra_match() into ↵YenHaoChen1-2/+2
detect_trap_match::detect_trap_match()
2023-01-04triggers: refactor: move textra_match() into ↵YenHaoChen1-2/+3
mcontrol_common_t::detect_memory_access_match()
2023-01-04triggers: refactor: move detect_trap_match() to trap_common_t from ↵YenHaoChen2-21/+3
itrigger_t/etrigger_t
2023-01-04triggers: refactor: create virtual function trap_common_t::simple_match()YenHaoChen1-2/+5
2023-01-04triggers: refactor: move get_action() to trap_common_t from ↵YenHaoChen1-4/+1
itrigger_t/etrigger_t
2023-01-04triggers: refactor: move get_dmode() to trap_common_t from itrigger_t/etrigger_tYenHaoChen1-2/+3
2023-01-04triggers: refactor: move action variable to trap_common_t from ↵YenHaoChen1-2/+1
itrigger_t/etrigger_t
2023-01-04triggers: refactor: move hit variable to trap_common_t from ↵YenHaoChen1-2/+1
itrigger_t/etrigger_t
2023-01-04triggers: refactor: move dmode variable to trap_common_t from ↵YenHaoChen1-2/+2
itrigger_t/etrigger_t
2023-01-04triggers: refactor: add empty parent trap_common_t class for itrigger_t and ↵YenHaoChen1-2/+5
etrigger_t
2023-01-03Delete --enable-misaligned configure optionAndrew Waterman3-24/+0
2023-01-03Respect --[no-]misaligned command-line flagAndrew Waterman2-19/+13
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