aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2018-01-31Passes smoke tests with --progsize=0no_progbufTim Newsome1-15/+82
2018-01-30WIP. Doesn't work.Tim Newsome2-40/+36
2018-01-29Update debug_definesTim Newsome3-53/+53
2018-01-18Support debug system bus access.Tim Newsome5-20/+230
2018-01-09Use new debug_defines.h.Tim Newsome1-19/+19
2018-01-08mem_t: Throw an error if zero-sized memory is requested (#168)Jonathan Neuschäfer2-0/+4
* mem_t: Throw an error if zero-sized memory is requested If for some reason the user requests a memory size of 0 megabytes, print a useful error message. * Check for overflow in memory size If the user passes in a large enough memory size (-m) that the size in bytes doesn't fit into size_t, catch this error in the make_mems function.
2018-01-03Add some missing RVC instructions to disassemblerAndrew Waterman1-0/+3
2017-12-18Merge pull request #165 from riscv/small_progbufTim Newsome7-484/+487
Add support for program buffer of size 2
2017-12-11Update debug_defines to latest version.Tim Newsome1-22/+48
2017-12-11Set impebreak.Tim Newsome2-1/+9
2017-12-11Update to latest debug_defines.h.Tim Newsome3-465/+411
2017-12-11Make progbuf a run-time option.Tim Newsome6-19/+42
Also add an implicit ebreak after the program buffer. This is not part of the spec, but hopefully it will be.
2017-11-27Rename badaddr to tvalAndrew Waterman5-25/+25
2017-11-27Rename sptbr to satpAndrew Waterman5-36/+36
2017-11-27Set tval to 0 on traps with no specified tvalAndrew Waterman2-5/+3
Simply not writing the register was not a conformant implementation.
2017-11-20Implement priv-1.11 interrupt-priority scheme (#161)Andrew Waterman1-1/+18
Closes #159. https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3
2017-11-20Fix commitlog. (#162)Christopher Celio1-5/+8
A regression caused any instruction with rd=x0 to not be emitted.
2017-11-15Merge pull request #156 from p12nGH/noncontiguous_hartsAndrew Waterman3-5/+31
Support for non-contiguous hartids
2017-11-15hartids knob description addedGleb Gagarin1-0/+1
2017-11-15Support for non-contiguous hartidsGleb Gagarin3-5/+30
2017-11-09Remove redundant U/S mode advertisementAndrew Waterman1-4/+0
2017-11-09H-mode no longer existsAndrew Waterman2-2/+0
It's supplanted by the hypervisor extension, which doesn't use the privilege encoding of 2; it still looks like supervisor (i.e. 1).
2017-11-09MPP is now WARLAndrew Waterman2-6/+23
2017-11-06Implement Q extension for disassembler (#153)Kito Cheng1-0/+36
2017-11-03Fix disassembly of c.li 0Andrew Waterman1-1/+1
Resolves #152
2017-11-03Merge pull request #151 from riscv/htif_dtsPalmer Dabbelt1-0/+3
Put HTIF in the device tree
2017-11-03Put HTIF in the device treePalmer Dabbelt1-0/+3
I wanted to actually put the address of the HTIF into the DTS, but that seems to be a bit too much work: since the HTIF addresses are just defined in an ELF file it's a bit awkward to make that work. Instead, I'm just putting a dummy HTIF key in the DTS.
2017-11-02Mask medeleg correctlyAndrew Waterman1-3/+7
2017-11-01Don't permit delegation of interrupts that M-mode should handleAndrew Waterman1-4/+3
2017-10-20Fix commit-log for Q extension, and for RV32 (#143)Andrew Waterman3-18/+53
* Fix commit-log for Q extension, and for RV32 The number of nibbles printed out now depends upon XLEN or FLEN, as appropriate. * Factor out FLEN calculation
2017-10-19Fix bus_t bug with devices at 0x0Evan Cox1-10/+30
Fix a bug that prevented bus_t from storing to, loading from, or finding a device that existed at address 0x0. Resolves: #135
2017-10-19Fix implementation of FMIN/FMAX NaN caseAndrew Waterman6-6/+12
If rd=rs1 or rd=rs2, the NaN check examined the wrong value.
2017-10-15Include math.h for NAN (#137)jar1-0/+1
commit 85c40db208db3e26f507dc6a74a5dc540b504b5c introduced a NAN dependency but did not include the math.h header
2017-10-10Merge pull request #129 from riscv/q-extensionAndrew Waterman263-1092/+11453
Implement Q extension
2017-09-28Implement Q extensionAndrew Waterman45-24/+258
2017-09-25Merge pull request #128 from riscv/resetTim Newsome1-1/+8
Fix debug reset.
2017-09-24Update SoftFloatAndrew Waterman218-1068/+11195
2017-09-21Actually let hartreset be set.Tim Newsome1-0/+1
2017-09-21Fix debug reset.Tim Newsome1-1/+7
ndmreset now resets all harts (instead of just the current hart), and hartreset resets the selected hart (instead of being ignored).
2017-09-21Fix corner case in repeated execution (#127)Tim Newsome2-4/+4
Specifically, don't print out the execution count if the same instruction is executed by different harts.
2017-09-21Fix comment typo. (#126)Tim Newsome1-1/+1
2017-09-12Merge pull request #123 from riscv/debug_interruptsTim Newsome1-1/+1
Don't take interrupts while in Debug Mode.
2017-09-12Don't take interrupts while in Debug Mode.Tim Newsome1-1/+1
2017-08-28Merge pull request #121 from riscv/debug_storeTim Newsome1-1/+13
Add a nice debug printf for debug_module_t::store
2017-08-28Add a nice debug printf for debug_module_t::storeTim Newsome1-1/+13
2017-08-11Merge pull request #119 from riscv/quietTim Newsome1-2/+2
Turn off debug module debug printfs.
2017-08-11Turn off debug module debug printfs.Tim Newsome1-2/+2
Nobody wants to see all that, and if they do they should recompile.
2017-08-10Correct c.li and c.lui disassembly (#118)Palmer Dabbelt1-2/+2
I currently get this disassembly 00004881 jr a7 but if I understand that's incorrect and I want 00004881 li a7, 0 If I'm reading the ISA manual correctly, the disassembler was just wrong here.
2017-08-10Merge pull request #117 from riscv/multicore_debugTim Newsome3-18/+12
Fix multicore debug.
2017-08-07Fix multicore debug.Tim Newsome3-18/+12
In an older implementation I was thinking of having different entry points for different harts, but that's no longer true. Also get rid of a bunch of trailing whitespace.
generated by cgit v1.1 at 2024-07-17 07:42:09 +0000