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2022-09-01Substantially increase context_t stack sizeincrease-stack-sizeAndrew Waterman1-1/+1
It's nearly free to do so, because it's just virtual address space. @davidbiancolin recently fell into this pit when using context_t with VCS.
2022-01-26Use unified ISA-string processing in spike-dasm and spikeWeiwei Li4-38/+37
2022-01-25Add more assertion for fcvt (#910)Yueh-Ting (eop) Chen1-0/+2
2022-01-23Merge pull request #908 from plctlab/fix-redifinition-csrsAndrew Waterman1-2/+0
fix redefinition of CSR_MCONTEXT and CSR_SCONTEXT
2022-01-22fix redefinition of CSR_MCONTEXT and CSR_SCONTEXTWeiwei Li1-2/+0
2022-01-19Fix HINVAL.VVMA and HINVAL.GVMA opcodesAndrew Waterman1-27/+204
The opcodes were incorrect in riscv-opcodes; now they match the spec.
2022-01-10Merge pull request #899 from riscv-software-src/rv32eAndrew Waterman5-37/+96
Add RV32E/RV64E base ISA support
2022-01-09Changes to be cleaner wrt. -WextraAndrew Waterman5-11/+10
h/t @jerinjoy See #901
2022-01-06Support RV32E/RV64E base ISAsAndrew Waterman5-20/+55
2022-01-06Parse RV32E/RV64E base ISA strings; improve error messagesAndrew Waterman1-15/+30
2022-01-06DRY in illegal-instruction descriptorsAndrew Waterman2-4/+11
2022-01-06DRY in selecting instruction functionsAndrew Waterman2-3/+5
2022-01-06Don't say "master" (#898)Tim Newsome3-18/+18
Requested by "LfX Security - Non Inclusive Language Alerts"
2021-12-29Disassemble Zbs instructionsAndrew Waterman1-0/+9
2021-12-27Update instruction vmandnot.mm, vmornot.mm -> vmandn.mm, vmorn.mm (#896)Yueh-Ting (eop) Chen7-14/+14
Refer to rvv-spec v1.0-rc2
2021-12-27Fix check for fcvt (#897)Yueh-Ting (eop) Chen1-9/+18
2021-12-23Fix check for fcvt (#894)Yueh-Ting (eop) Chen1-2/+2
2021-12-21Add missing check for floating-point merge instructions (#893)Yueh-Ting (eop) Chen1-4/+6
2021-12-17Add disassembler support for `unimp' (#886)Tsukasa #01 (a4lg)1-0/+3
Now it disassembles 0x0000 (invalid encoding of c.addi4spn) as c.unimp (RVC). Non-RVC variant of unimp pseudoinstruction (0xc0001073) is also implemented.
2021-12-17Merge pull request #881 from eopXD/simplify-float-convertAndrew Waterman23-437/+322
Simplify float convert instructions
2021-12-17Now on 1.1.1-devAndrew Waterman1-1/+1
2021-12-171.1.0 releasev1.1.0Andrew Waterman3-5/+20
2021-12-16TSR is read-only 0 when S-mode is not supported. (#890)sven1-1/+2
According the privileged spec, TSR is read-only 0 when S-mode is not supported. (https://github.com/riscv/riscv-isa-manual/blob/56515289e5999512fe578cdddf861b730d790018/src/machine.tex#L860-L861)
2021-12-12Fix minor type-o (#885)Yueh-Ting (eop) Chen1-2/+2
2021-12-09P-ext v.0.9.11. update (#883)marcfedorow4-4/+4
2021-12-09Simplfy vfmv_v_f (#884)Yueh-Ting (eop) Chen1-30/+3
2021-12-09Simplify vfwcvteopXD8-195/+112
2021-12-09Simplfy vfcvteopXD7-66/+70
2021-12-09Simplify vfncvteopXD9-182/+146
2021-12-08Have vd.v unexposedeopXD1-3/+3
2021-12-07Add 'Zfhmin' extension (#880)Tsukasa #01 (a4lg)12-13/+16
Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating point) extension, consisting only of data transfer and conversion instructions. This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin" as a multi-letter extension and adjusts feature gate for data transfer / conversion instructions. * FLH / FSH * FMV.X.H / FMV.H.X * FCVT.S.H / FCVT.H.S * FCVT.D.H / FCVT.H.D (if 'D' extension is also present) * FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)
2021-12-07Merge pull request #879 from eopXD/simply-instsAndrew Waterman18-151/+153
Simply floating point parameters and merge operations
2021-12-07Simplify vadc and vsbc (#876)Yueh-Ting (eop) Chen6-36/+15
2021-12-07Merge pull request #868 from eopXD/simplify-narrowing-instAndrew Waterman13-65/+72
Simplify narrowing instruction
2021-12-07Simplify vwmulsu_vv and vwmulsu_vx (#861)Yueh-Ting (eop) Chen2-22/+2
Leverage macro VI_WIDE_OP_AND_ASSIGN_MIX
2021-12-08Simplify vmerge, vfmergeeopXD8-78/+75
2021-12-08Simplify floating point compare instructionseopXD11-43/+55
2021-12-08Simply parameters for floating-point instructionseopXD2-33/+26
2021-12-06Simplify vmadc and vmsbc (#877)Yueh-Ting (eop) Chen6-53/+24
2021-12-05page fault when PTE_N bit set and not EXT_SVNAPOT (#875)John Ingalls1-0/+4
2021-12-04page fault when PTE_PBMT bits set and not EXT_SVPBMT (#874)John Ingalls1-0/+4
2021-12-01Merge pull request #871 from a4lg/string-handlingAndrew Waterman1-14/+12
Improve string handling (ISA string)
2021-12-02Parse isa_string as C-style stringTsukasa OI1-2/+3
On C++11 and later, std::string is guaranteed to be null-terminated. However, `*(str.end())` is NOT guaranteed to be '\0'. So, we parse ISA string using C-style string buffer (raw pointers).
2021-12-02Use strtolower in parse_varch_stringTsukasa OI1-12/+9
2021-11-30Simplify mulhsu (#870)Yueh-Ting (eop) Chen3-72/+51
2021-11-29Merge pull request #869 from scottj97/badgpaAndrew Waterman1-48/+53
Take guest page fault if guest PA out of bounds
2021-11-29Revert "Simplify vmulhsu (#863)"Andrew Waterman2-6/+72
This reverts commit 1a5b2d9dda8741e98444289135e0fbcb2c3f5740, which is buggy (the vs1 argument is being sign-extended).
2021-11-29Reindent s2xlate()Scott Johnson1-49/+49
2021-11-29Raise guest page fault if GPA is out of rangeScott Johnson1-0/+5
Based on this statement from priv spec 5.5.1 (regarding Sv39x4): "Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs."
2021-11-28Have nclip_{wv/wx/wi} use different macroseopXD7-53/+60
This allows them to share PARAM macro with narrowing right-shift instructions. Rename VV_NSHIFT_PARAMS -> VV_NARROW_PARAMS so nclip, nsra, nsrl can share it. (Same goes to VX_NSHIFT_PARAMS and VI_NSHIFT_PARAMS)
generated by cgit v1.1 at 2024-09-18 08:15:34 +0000