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AgeCommit message (Expand)AuthorFilesLines
2014-02-07Clear EVEC LSBs, which kindly prevents a segfaultAndrew Waterman1-2/+2
2014-02-06Fix disassembly of JALAndrew Waterman1-1/+1
2014-02-06commit missing definitions for uarch countersYunsup Lee1-0/+56
2014-02-03Move half precision instructions, add vfmsv, vfmvvQuan Nguyen48-137/+265
2014-01-31Fix linking on DarwinAndrew Waterman3-4/+3
2014-01-28Disasm now translates xor x0,x0,x0 as a machine-generated bubble ("-").Christopher Celio1-0/+1
2014-01-28Force extension loaders to be linked inAndrew Waterman2-6/+10
2014-01-26Enable runtime loading of dynamic library with --extlibAndrew Waterman5-158/+160
2014-01-26Prefer libraries located in current directoryAndrew Waterman1-4/+4
2014-01-26Eliminate hwacha <-> riscv circular dependenceAndrew Waterman11-110/+170
2014-01-26Link subproject dynamic libraries correctlyAndrew Waterman1-7/+11
2014-01-25Merge softfloat_riscv into softfloatAndrew Waterman18-70/+13
2014-01-24Require libdl for dynamic linking at runtimeAndrew Waterman3-15/+68
2014-01-24Disassemble amoxorAndrew Waterman1-0/+2
2014-01-24Build and use shared libraries onlyAndrew Waterman3-5/+6
2014-01-24Build and use shared librariesAndrew Waterman3-45/+45
2014-01-24Handle CSR permissions correctlyAndrew Waterman2-6/+10
2014-01-21Use auto-generated trap cause numbersAndrew Waterman2-26/+52
2014-01-20Merge branch 'confprec'Quan Nguyen78-0/+353
2014-01-16Initialize tohost and fromhost to zeroAndrew Waterman1-2/+5
2014-01-13Improve performance for branchy codeAndrew Waterman14-85/+131
2013-12-17Speed things up quite a bitAndrew Waterman7-79/+118
2013-12-09New RDCYCLE encodingAndrew Waterman9-38/+39
2013-11-29Remove debug printf in vsetprecconfprecQuan Nguyen1-1/+0
2013-11-29Add vsetprec instruction prototypeQuan Nguyen5-0/+17
2013-11-25Update to new privileged ISAAndrew Waterman30-402/+785
2013-11-24Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEADQuan Nguyen7-4/+9
2013-11-21fix slli/slliw encoding bugYunsup Lee2-4/+4
2013-11-05add accelerator disabled causeYunsup Lee1-0/+1
2013-11-05correctly trap when SR_EA is disabledYunsup Lee4-0/+4
2013-11-04Fix declaration of half-precision instructionsAlbert Ou2-0/+2
2013-11-04Re-add Hwacha header fileAlbert Ou1-0/+1
2013-11-04Implement "half-baked" half-precision instruction subset for HwachaAlbert Ou39-2/+336
2013-11-04Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into confprecAlbert Ou30-180/+463
2013-10-28include stdexceptYunsup Lee1-0/+1
2013-10-28Pass target machine's return code back to OSAndrew Waterman3-3/+4
2013-10-27Add missing fcvt opcodes through riscv-opcodesQuan Nguyen1-37/+4
2013-10-21clarify vxcptsave/vxctkill semanticsYunsup Lee3-3/+7
2013-10-18implement vxcptsave/vxcptrestoreYunsup Lee4-3/+82
2013-10-18clean up SR_EA, the enable accelerator bit in status regYunsup Lee2-5/+4
2013-10-18more hwacha supervisor stuffYunsup Lee6-17/+21
2013-10-18refactor disassembler, and add hwacha disassemblerYunsup Lee17-144/+347
2013-10-18can't execute frsr/fssr on utYunsup Lee3-4/+0
2013-10-18or into control thread's fp exceptionsYunsup Lee1-4/+0
2013-10-17Add empty opcode header files for half-precisionQuan Nguyen34-4/+37
2013-10-17catch trap_illegal_instruction in hwachaYunsup Lee1-0/+4
2013-10-17add hwacha exception supportYunsup Lee16-38/+213
2013-10-17fix custom-1 rocc encodingYunsup Lee1-1/+1
2013-10-16fix maxvl calc logicYunsup Lee1-1/+5
2013-10-16use reset virtual methodYunsup Lee3-4/+5
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