diff options
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/debug_module.cc | 11 | ||||
-rw-r--r-- | riscv/debug_module.h | 4 | ||||
-rw-r--r-- | riscv/sim.cc | 6 | ||||
-rw-r--r-- | riscv/sim.h | 2 |
4 files changed, 12 insertions, 11 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 0c3e927..20419b1 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -32,13 +32,15 @@ static unsigned field_width(unsigned n) ///////////////////////// debug_module_t debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits, - bool require_authentication, unsigned abstract_rti, bool support_hasel) : + bool require_authentication, unsigned abstract_rti, bool support_hasel, + bool support_abstract_csr_access) : nprocs(sim->nprocs()), progbufsize(progbufsize), program_buffer_bytes(4 + 4*progbufsize), max_bus_master_bits(max_bus_master_bits), require_authentication(require_authentication), abstract_rti(abstract_rti), + support_abstract_csr_access(support_abstract_csr_access), debug_progbuf_start(debug_data_start - program_buffer_bytes), debug_abstract_start(debug_progbuf_start - debug_abstract_size*4), custom_base(0), @@ -585,9 +587,7 @@ bool debug_module_t::perform_abstract_command() unsigned i = 0; if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) { - if (regno < 0x1000 && progbufsize < 2) { - // Make the debugger use the program buffer if it's available, so it - // can test both use cases. + if (regno < 0x1000 && support_abstract_csr_access) { write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH)); if (write) { @@ -642,9 +642,6 @@ bool debug_module_t::perform_abstract_command() } } else if (regno >= 0x1020 && regno < 0x1040) { - // Don't force the debugger to use progbuf if it exists, so the - // debugger has to make the decision not to use abstract commands to - // access 64-bit FPRs on 32-bit targets. unsigned fprnum = regno - 0x1020; if (write) { diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 5bd9e66..f24a097 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -95,7 +95,8 @@ class debug_module_t : public abstract_device_t */ debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits, bool require_authentication, - unsigned abstract_rti, bool support_hasel); + unsigned abstract_rti, bool support_hasel, + bool support_abstract_csr_access); ~debug_module_t(); void add_device(bus_t *bus); @@ -127,6 +128,7 @@ class debug_module_t : public abstract_device_t unsigned max_bus_master_bits; bool require_authentication; unsigned abstract_rti; + bool support_abstract_csr_access; static const unsigned debug_data_start = 0x380; unsigned debug_progbuf_start; diff --git a/riscv/sim.cc b/riscv/sim.cc index db68930..3cd29af 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -29,12 +29,14 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, const std::vector<std::string>& args, std::vector<int> const hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication, - suseconds_t abstract_delay_usec, bool support_hasel) + suseconds_t abstract_delay_usec, bool support_hasel, + bool support_abstract_csr_access) : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))), start_pc(start_pc), current_step(0), current_proc(0), debug(false), histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits, require_authentication, - abstract_delay_usec, support_hasel) + abstract_delay_usec, support_hasel, + support_abstract_csr_access) { signal(SIGINT, &handle_signal); diff --git a/riscv/sim.h b/riscv/sim.h index ef3e780..d1c7a37 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -26,7 +26,7 @@ public: const std::vector<std::string>& args, const std::vector<int> hartids, unsigned progsize, unsigned max_bus_master_bits, bool require_authentication, suseconds_t abstract_delay_usec, - bool support_hasel); + bool support_hasel, bool support_abstract_csr_access); ~sim_t(); // run the simulation to completion |