diff options
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 3 | ||||
-rw-r--r-- | riscv/interactive.cc | 16 | ||||
-rw-r--r-- | riscv/processor.cc | 16 | ||||
-rw-r--r-- | riscv/processor.h | 2 |
4 files changed, 16 insertions, 21 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 3f145f5..72ad286 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -285,7 +285,8 @@ private: #define sext32(x) ((sreg_t)(int32_t)(x)) #define zext32(x) ((reg_t)(uint32_t)(x)) #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen)) -#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen)) +#define zext(x, pos) (((reg_t)(x) << (64-(pos))) >> (64-(pos))) +#define zext_xlen(x) zext(x, xlen) #define set_pc(x) \ do { p->check_pc_alignment(x); \ diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 22929d4..5ed87d3 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -184,8 +184,7 @@ void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string processor_t *p = get_core(args[0]); int max_xlen = p->get_max_xlen(); - fprintf(stderr, max_xlen==32 ? "0x%08" PRIx64 "\n" : - "0x%016" PRIx64 "\n", ERASE_32MSB(max_xlen,get_pc(args))); + fprintf(stderr, "0x%0*" PRIx64 "\n", max_xlen/4, zext(get_pc(args), max_xlen)); } reg_t sim_t::get_reg(const std::vector<std::string>& args) @@ -288,14 +287,14 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin // Show all the regs! for (int r = 0; r < NXPR; ++r) { - fprintf(stderr, max_xlen==32 ? "%-4s: 0x%08" PRIx64 " " : - "%-4s: 0x%016" PRIx64 " ", xpr_name[r], ERASE_32MSB(max_xlen,p->get_state()->XPR[r])); + fprintf(stderr, "%-4s: 0x%0*" PRIx64 " ", xpr_name[r], max_xlen/4, + zext(p->get_state()->XPR[r], max_xlen)); if ((r + 1) % 4 == 0) fprintf(stderr, "\n"); } - } else - fprintf(stderr, max_xlen==32 ? "0x%08" PRIx64 "\n" : - "0x%016" PRIx64 "\n", ERASE_32MSB(max_xlen,get_reg(args))); + } else { + fprintf(stderr, "0x%0*" PRIx64 "\n", max_xlen/4, zext(get_reg(args), max_xlen)); + } } union fpr @@ -373,8 +372,7 @@ void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::strin { int max_xlen = procs[0]->get_max_xlen(); - fprintf(stderr, max_xlen==32 ? "0x%08" PRIx64 "\n" : - "0x%016" PRIx64 "\n", ERASE_32MSB(max_xlen,get_mem(args))); + fprintf(stderr, "0x%0*" PRIx64 "\n", max_xlen/4, zext(get_mem(args), max_xlen)); } void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args) diff --git a/riscv/processor.cc b/riscv/processor.cc index 0b579d8..d6e47af 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -667,13 +667,11 @@ void processor_t::enter_debug_mode(uint8_t cause) void processor_t::take_trap(trap_t& t, reg_t epc) { if (debug) { - fprintf(log_file, max_xlen==32 ? "core %3d: exception %s, epc 0x%08" PRIx64 "\n" : - "core %3d: exception %s, epc 0x%016" PRIx64 "\n", - id, t.name(), ERASE_32MSB(max_xlen,epc)); + fprintf(log_file, "core %3d: exception %s, epc 0x%0*" PRIx64 "\n", + id, t.name(), max_xlen/4, zext(epc, max_xlen)); if (t.has_tval()) - fprintf(log_file, max_xlen==32 ? "core %3d: tval 0x%08" PRIx64 "\n" : - "core %3d: tval 0x%016" PRIx64 "\n", - id, ERASE_32MSB(max_xlen,t.get_tval())); + fprintf(log_file, "core %3d: tval 0x%0*" PRIx64 "\n", + id, max_xlen/4, zext(t.get_tval(), max_xlen)); } if (state.debug_mode) { @@ -782,9 +780,9 @@ void processor_t::disasm(insn_t insn) fprintf(log_file, "core %3d: Executed %" PRIx64 " times\n", id, executions); } - fprintf(log_file, max_xlen==32 ? "core %3d: 0x%08" PRIx64 " (0x%08" PRIx64 ") %s\n" : - "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n", - id, ERASE_32MSB(max_xlen,state.pc), bits, disassembler->disassemble(insn).c_str()); + fprintf(log_file, "core %3d: 0x%0*" PRIx64 " (0x%08" PRIx64 ") %s\n", + id, max_xlen/4, zext(state.pc, max_xlen), bits, + disassembler->disassemble(insn).c_str()); last_pc = state.pc; last_bits = bits; executions = 1; diff --git a/riscv/processor.h b/riscv/processor.h index ad6e892..1cc6185 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -553,6 +553,4 @@ reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \ proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name,archen}); -#define ERASE_32MSB(m,n) (m==32 ? n & 0xffffffff : n) - #endif |