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-rw-r--r--riscv/sim.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h
index 9a0a10b..257de5b 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -24,6 +24,8 @@ public:
// used for MMIO addresses
virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0;
virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
+ // Callback for processors to let the simulation know they were reset.
+ virtual void proc_reset(unsigned id) = 0;
};
// this class encapsulates the processors and memory in a RISC-V machine.
@@ -49,6 +51,9 @@ public:
processor_t* get_core(size_t i) { return procs.at(i); }
unsigned nprocs() const { return procs.size(); }
+ // Callback for processors to let the simulation know they were reset.
+ void proc_reset(unsigned id);
+
private:
std::vector<std::pair<reg_t, mem_t*>> mems;
mmu_t* debug_mmu; // debug port into main memory