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-rw-r--r--riscv/processor.cc7
1 files changed, 3 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index ae02165..203394b 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -360,10 +360,9 @@ void processor_t::set_csr(int which, reg_t val)
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+ reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT
+ | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT
+ | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT;
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}