diff options
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 40a435f..8b9ff9b 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -52,7 +52,7 @@ public: #define RISCV_XLATE_VIRT (1U << 0) #define RISCV_XLATE_VIRT_HLVX (1U << 1) - inline reg_t misaligned_load(reg_t addr, size_t size, uint32_t xlate_flags) + inline reg_t misaligned_load(reg_t addr, size_t UNUSED size, uint32_t xlate_flags) { #ifdef RISCV_ENABLE_MISALIGNED reg_t res = 0; @@ -72,7 +72,7 @@ public: #endif } - inline void misaligned_store(reg_t addr, reg_t data, size_t size, uint32_t xlate_flags, bool actually_store=true) + inline void misaligned_store(reg_t addr, reg_t UNUSED data, size_t UNUSED size, uint32_t xlate_flags, bool UNUSED actually_store=true) { #ifdef RISCV_ENABLE_MISALIGNED for (size_t i = 0; i < size; i++) { @@ -91,7 +91,7 @@ public: } #ifndef RISCV_ENABLE_COMMITLOG -# define READ_MEM(addr, size) ({}) +# define READ_MEM(addr, size) ((void)(addr), (void)(size)) #else # define READ_MEM(addr, size) \ proc->state.log_mem_read.push_back(std::make_tuple(addr, 0, size)); @@ -159,7 +159,7 @@ public: load_func(int64, guest_load, RISCV_XLATE_VIRT) #ifndef RISCV_ENABLE_COMMITLOG -# define WRITE_MEM(addr, value, size) ({}) +# define WRITE_MEM(addr, value, size) ((void)(addr), (void)(value), (void)(size)) #else # define WRITE_MEM(addr, val, size) \ proc->state.log_mem_write.push_back(std::make_tuple(addr, val, size)); @@ -277,7 +277,7 @@ public: convert_load_traps_to_store_traps({ const reg_t vaddr = addr & ~(blocksz - 1); const reg_t paddr = translate(vaddr, blocksz, LOAD, 0); - if (auto host_addr = sim->addr_to_mem(paddr)) { + if (sim->addr_to_mem(paddr)) { if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) tracer.clean_invalidate(paddr, blocksz, clean, inval); } else { |