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-rw-r--r--riscv/insns/vslide1down_vx.h5
-rw-r--r--riscv/insns/vslide1up_vx.h6
-rw-r--r--riscv/insns/vslidedown_vi.h10
-rw-r--r--riscv/insns/vslidedown_vx.h14
-rw-r--r--riscv/insns/vslideup_vi.h6
-rw-r--r--riscv/insns/vslideup_vx.h6
6 files changed, 37 insertions, 10 deletions
diff --git a/riscv/insns/vslide1down_vx.h b/riscv/insns/vslide1down_vx.h
index 0069df7..04e2540 100644
--- a/riscv/insns/vslide1down_vx.h
+++ b/riscv/insns/vslide1down_vx.h
@@ -1,4 +1,9 @@
//vslide1down.vx vd, vs2, rs1
+require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+if (P.VU.vlmul > 1 && insn.v_vm() == 0)
+ require(insn.rd() != 0);
+
VI_LOOP_BASE
if (i != vl - 1) {
switch (sew) {
diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h
index 50cc503..69ce0fd 100644
--- a/riscv/insns/vslide1up_vx.h
+++ b/riscv/insns/vslide1up_vx.h
@@ -1,8 +1,10 @@
//vslide1up.vx vd, vs2, rs1
-if (insn.v_vm() == 0)
+require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+require(insn.rd() != insn.rs2());
+if (P.VU.vlmul > 1 && insn.v_vm() == 0)
require(insn.rd() != 0);
-VI_CHECK_SS
VI_LOOP_BASE
if (i != 0) {
if (sew == e8) {
diff --git a/riscv/insns/vslidedown_vi.h b/riscv/insns/vslidedown_vi.h
index c21c5f2..dd58c1e 100644
--- a/riscv/insns/vslidedown_vi.h
+++ b/riscv/insns/vslidedown_vi.h
@@ -1,8 +1,14 @@
// vslidedown.vi vd, vs2, rs1
-VI_LOOP_BASE
+require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+if (P.VU.vlmul > 1 && insn.v_vm() == 0)
+ require(insn.rd() != 0);
+
const reg_t sh = insn.v_zimm5();
-bool is_valid = (i + sh) < P.VU.vlmax;
+VI_LOOP_BASE
+
reg_t offset = 0;
+bool is_valid = (i + sh) < P.VU.vlmax;
if (is_valid) {
offset = sh;
diff --git a/riscv/insns/vslidedown_vx.h b/riscv/insns/vslidedown_vx.h
index 251740c..9881e0e 100644
--- a/riscv/insns/vslidedown_vx.h
+++ b/riscv/insns/vslidedown_vx.h
@@ -1,11 +1,17 @@
//vslidedown.vx vd, vs2, rs1
+require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+if (P.VU.vlmul > 1 && insn.v_vm() == 0)
+ require(insn.rd() != 0);
+
+const reg_t sh = RS1;
VI_LOOP_BASE
-reg_t offset = RS1 == (reg_t)-1 ? ((RS1 & (P.VU.vlmax * 2 - 1)) + i) : RS1;
-bool is_valid = offset < P.VU.vlmax;
+reg_t offset = 0;
+bool is_valid = (i + sh) < P.VU.vlmax;
-if (!is_valid) {
- offset = 0;
+if (is_valid) {
+ offset = sh;
}
switch (sew) {
diff --git a/riscv/insns/vslideup_vi.h b/riscv/insns/vslideup_vi.h
index 4135b20..64b4aca 100644
--- a/riscv/insns/vslideup_vi.h
+++ b/riscv/insns/vslideup_vi.h
@@ -1,8 +1,10 @@
// vslideup.vi vd, vs2, rs1
-if (insn.v_vm() == 0)
+require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+require(insn.rd() != insn.rs2());
+if (P.VU.vlmul > 1 && insn.v_vm() == 0)
require(insn.rd() != 0);
-VI_CHECK_SS
const reg_t offset = insn.v_zimm5();
VI_LOOP_BASE
if (P.VU.vstart < offset && i < offset)
diff --git a/riscv/insns/vslideup_vx.h b/riscv/insns/vslideup_vx.h
index bf73fcd..063c061 100644
--- a/riscv/insns/vslideup_vx.h
+++ b/riscv/insns/vslideup_vx.h
@@ -1,4 +1,10 @@
//vslideup.vx vd, vs2, rs1
+require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
+require((insn.rd() & (P.VU.vlmul - 1)) == 0);
+require(insn.rd() != insn.rs2());
+if (P.VU.vlmul > 1 && insn.v_vm() == 0)
+ require(insn.rd() != 0);
+
const reg_t offset = RS1;
VI_LOOP_BASE
if (P.VU.vstart < offset && i < offset)