diff options
| -rw-r--r-- | riscv/debug_rom.h (renamed from debug_rom/debug_rom.c) | 4 | ||||
| -rw-r--r-- | riscv/debug_rom/Makefile (renamed from debug_rom/Makefile) | 2 | ||||
| -rwxr-xr-x | riscv/debug_rom/debug_rom.S (renamed from debug_rom/debug_rom.S) | 0 | ||||
| -rw-r--r-- | riscv/debug_rom/debug_rom.h | 2 | ||||
| -rw-r--r-- | riscv/debug_rom/link.ld (renamed from debug_rom/link.ld) | 0 | ||||
| -rw-r--r-- | riscv/decode.h | 7 | ||||
| -rw-r--r-- | riscv/mmu.cc | 1 | ||||
| -rw-r--r-- | riscv/processor.cc | 7 | ||||
| -rw-r--r-- | riscv/sim.cc | 9 |
9 files changed, 25 insertions, 7 deletions
diff --git a/debug_rom/debug_rom.c b/riscv/debug_rom.h index 9d67df5..d2837ac 100644 --- a/debug_rom/debug_rom.c +++ b/riscv/debug_rom.h @@ -1,4 +1,4 @@ -unsigned char debug_rom_raw[] = { +static unsigned char debug_rom_raw[] = { 0x6f, 0x00, 0x40, 0x05, 0xf3, 0x24, 0x00, 0xf1, 0x23, 0x24, 0x90, 0x10, 0xf3, 0x24, 0x00, 0x79, 0x93, 0xf4, 0x04, 0x40, 0x63, 0x94, 0x04, 0x08, 0xf3, 0x24, 0x00, 0xf0, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0x43, @@ -15,4 +15,4 @@ unsigned char debug_rom_raw[] = { 0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x04, 0x40, 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfc }; -unsigned int debug_rom_raw_len = 172; +static unsigned int debug_rom_raw_len = 172; diff --git a/debug_rom/Makefile b/riscv/debug_rom/Makefile index 17cc95e..ff37a29 100644 --- a/debug_rom/Makefile +++ b/riscv/debug_rom/Makefile @@ -7,7 +7,7 @@ OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy %.o: %.S $(CC) -c $< -debug_rom.c: debug_rom.raw +debug_rom.cc: debug_rom.raw xxd -i $^ > $@ debug_rom.raw: debug_rom diff --git a/debug_rom/debug_rom.S b/riscv/debug_rom/debug_rom.S index 230f4b4..230f4b4 100755 --- a/debug_rom/debug_rom.S +++ b/riscv/debug_rom/debug_rom.S diff --git a/riscv/debug_rom/debug_rom.h b/riscv/debug_rom/debug_rom.h new file mode 100644 index 0000000..a99534e --- /dev/null +++ b/riscv/debug_rom/debug_rom.h @@ -0,0 +1,2 @@ +extern unsigned char *debug_rom_raw; +extern unsigned int debug_rom_raw_len; diff --git a/debug_rom/link.ld b/riscv/debug_rom/link.ld index 356099c..356099c 100644 --- a/debug_rom/link.ld +++ b/riscv/debug_rom/link.ld diff --git a/riscv/decode.h b/riscv/decode.h index d1254ee..b59ee78 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -14,6 +14,7 @@ #include "config.h" #include "common.h" #include <cinttypes> +#include "debug_rom.h" typedef int64_t sreg_t; typedef uint64_t reg_t; @@ -236,7 +237,9 @@ private: #define DCSR_CAUSE_STEPPED 4 #define DCSR_CAUSE_HALT 5 -#define DEBUG_RAM 0xfffffc00 // TODO: 0x400 -#define DEBUG_ROM_ENTRY 0xfffff800 // TODO: 0x800 +#define DEBUG_RAM_START 0xfffffffffffffc00 // TODO: 0x400 +#define DEBUG_RAM_END (DEBUG_RAM_START + 64) +#define DEBUG_ROM_START 0xfffffffffffff800 // TODO: 0x800 +#define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len) #endif diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 0113443..5fb72bf 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -54,6 +54,7 @@ reg_t mmu_t::translate(reg_t addr, access_type type) const uint16_t* mmu_t::fetch_slow_path(reg_t addr) { reg_t paddr = translate(addr, FETCH); + if (sim->addr_is_mem(paddr)) { refill_tlb(addr, paddr, FETCH); return (const uint16_t*)sim->addr_to_mem(paddr); diff --git a/riscv/processor.cc b/riscv/processor.cc index 4ef8e02..7c5c0fb 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -199,9 +199,13 @@ void processor_t::set_privilege(reg_t prv) void processor_t::enter_debug_mode(uint8_t cause) { + fprintf(stderr, "enter_debug_mode(%d)\n", cause); state.dcsr.cause = cause; + state.dcsr.prv = state.prv; + state.prv = PRV_M; state.dpc = state.pc; - state.pc = DEBUG_ROM_ENTRY; + state.pc = DEBUG_ROM_START; + debug = true; // TODO } void processor_t::take_trap(trap_t& t, reg_t epc) @@ -365,6 +369,7 @@ void processor_t::set_csr(int which, reg_t val) case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; case DCSR_ADDRESS: + // TODO: Use get_field style state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET; state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET; // TODO: ndreset and fullreset diff --git a/riscv/sim.cc b/riscv/sim.cc index 095c2d9..5cf2646 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -41,11 +41,18 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n", (unsigned long)memsz, (unsigned long)memsz0); + /* Copy Debug ROM into the end of the allocated block, because we surely + * didn't succeed in allocation 0xfffffffff800 bytes. */ + /* TODO: Once everything uses the new memory map, just put this at the + * address that it actually belongs at. */ + memcpy(mem + memsz - debug_rom_raw_len, debug_rom_raw, debug_rom_raw_len); + debug_mmu = new mmu_t(this, NULL); for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(isa, this, i); - procs[i]->enter_debug_mode(DCSR_CAUSE_HALT); + if (halted) + procs[i]->enter_debug_mode(DCSR_CAUSE_HALT); } rtc.reset(new rtc_t(procs)); |