diff options
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3206ed0..8347b9d 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -329,7 +329,7 @@ void processor_t::set_csr(int which, reg_t val) break; } case CSR_MIPI: { - state.mip |= MIP_MSIP; + state.mip = set_field(state.mip, MIP_MSIP, val & 1); break; } case CSR_MIE: { |