diff options
| -rw-r--r-- | riscv/encoding.h | 44 | ||||
| -rw-r--r-- | riscv/processor.cc | 28 | ||||
| -rw-r--r-- | riscv/riscv.mk.in | 7 | ||||
| -rw-r--r-- | spike_main/disasm.cc | 10 |
4 files changed, 42 insertions, 47 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 8620092..7216275 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1124,14 +1124,14 @@ #define MASK_VNCLIPU_VX 0xfc00707f #define MATCH_VNCLIP_VX 0xbc004057 #define MASK_VNCLIP_VX 0xfc00707f -#define MATCH_VWSMACCU_VX 0xf0004057 -#define MASK_VWSMACCU_VX 0xfc00707f -#define MATCH_VWSMACC_VX 0xf4004057 -#define MASK_VWSMACC_VX 0xfc00707f -#define MATCH_VWSMACCUS_VX 0xf8004057 -#define MASK_VWSMACCUS_VX 0xfc00707f -#define MATCH_VWSMACCSU_VX 0xfc004057 -#define MASK_VWSMACCSU_VX 0xfc00707f +#define MATCH_VQMACCU_VX 0xf0004057 +#define MASK_VQMACCU_VX 0xfc00707f +#define MATCH_VQMACC_VX 0xf4004057 +#define MASK_VQMACC_VX 0xfc00707f +#define MATCH_VQMACCUS_VX 0xf8004057 +#define MASK_VQMACCUS_VX 0xfc00707f +#define MATCH_VQMACCSU_VX 0xfc004057 +#define MASK_VQMACCSU_VX 0xfc00707f #define MATCH_VADD_VV 0x57 #define MASK_VADD_VV 0xfc00707f #define MATCH_VSUB_VV 0x8000057 @@ -1212,12 +1212,12 @@ #define MASK_VDOTU_VV 0xfc00707f #define MATCH_VDOT_VV 0xe4000057 #define MASK_VDOT_VV 0xfc00707f -#define MATCH_VWSMACCU_VV 0xf0000057 -#define MASK_VWSMACCU_VV 0xfc00707f -#define MATCH_VWSMACC_VV 0xf4000057 -#define MASK_VWSMACC_VV 0xfc00707f -#define MATCH_VWSMACCSU_VV 0xfc000057 -#define MASK_VWSMACCSU_VV 0xfc00707f +#define MATCH_VQMACCU_VV 0xf0000057 +#define MASK_VQMACCU_VV 0xfc00707f +#define MATCH_VQMACC_VV 0xf4000057 +#define MASK_VQMACC_VV 0xfc00707f +#define MATCH_VQMACCSU_VV 0xfc000057 +#define MASK_VQMACCSU_VV 0xfc00707f #define MATCH_VADD_VI 0x3057 #define MASK_VADD_VI 0xfc00707f #define MATCH_VRSUB_VI 0xc003057 @@ -1556,6 +1556,7 @@ #define CSR_HPMCOUNTER31 0xc1f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 @@ -2228,10 +2229,10 @@ DECLARE_INSN(vnsrl_vx, MATCH_VNSRL_VX, MASK_VNSRL_VX) DECLARE_INSN(vnsra_vx, MATCH_VNSRA_VX, MASK_VNSRA_VX) DECLARE_INSN(vnclipu_vx, MATCH_VNCLIPU_VX, MASK_VNCLIPU_VX) DECLARE_INSN(vnclip_vx, MATCH_VNCLIP_VX, MASK_VNCLIP_VX) -DECLARE_INSN(vwsmaccu_vx, MATCH_VWSMACCU_VX, MASK_VWSMACCU_VX) -DECLARE_INSN(vwsmacc_vx, MATCH_VWSMACC_VX, MASK_VWSMACC_VX) -DECLARE_INSN(vwsmaccus_vx, MATCH_VWSMACCUS_VX, MASK_VWSMACCUS_VX) -DECLARE_INSN(vwsmaccsu_vx, MATCH_VWSMACCSU_VX, MASK_VWSMACCSU_VX) +DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX) +DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX) +DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX) +DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX) DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) @@ -2272,9 +2273,9 @@ DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV) DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV) -DECLARE_INSN(vwsmaccu_vv, MATCH_VWSMACCU_VV, MASK_VWSMACCU_VV) -DECLARE_INSN(vwsmacc_vv, MATCH_VWSMACC_VV, MASK_VWSMACC_VV) -DECLARE_INSN(vwsmaccsu_vv, MATCH_VWSMACCSU_VV, MASK_VWSMACCSU_VV) +DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV) +DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV) +DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV) DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) @@ -2470,6 +2471,7 @@ DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) DECLARE_CSR(vl, CSR_VL) DECLARE_CSR(vtype, CSR_VTYPE) +DECLARE_CSR(vlenb, CSR_VLENB) DECLARE_CSR(sstatus, CSR_SSTATUS) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) diff --git a/riscv/processor.cc b/riscv/processor.cc index 21e51f8..bd30bc6 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -456,10 +456,10 @@ vectorUnit_t::vectorUnit_t() : MATCH_VNSRA_VX, MATCH_VNCLIPU_VX, MATCH_VNCLIP_VX, - MATCH_VWSMACCU_VX, - MATCH_VWSMACC_VX, - MATCH_VWSMACCSU_VX, - MATCH_VWSMACCUS_VX, + MATCH_VQMACCU_VX, + MATCH_VQMACC_VX, + MATCH_VQMACCSU_VX, + MATCH_VQMACCUS_VX, MATCH_VADD_VV, MATCH_VSUB_VV, MATCH_VMINU_VV, @@ -502,9 +502,9 @@ vectorUnit_t::vectorUnit_t() : MATCH_VWREDSUM_VS, MATCH_VDOTU_VV, MATCH_VDOT_VV, - MATCH_VWSMACCU_VV, - MATCH_VWSMACC_VV, - MATCH_VWSMACCSU_VV, + MATCH_VQMACCU_VV, + MATCH_VQMACC_VV, + MATCH_VQMACCSU_VV, MATCH_VADD_VI, MATCH_VRSUB_VI, MATCH_VAND_VI, @@ -816,10 +816,10 @@ vectorUnit_t::vectorUnit_t() : MATCH_VNSRA_VX, MATCH_VNCLIPU_VX, MATCH_VNCLIP_VX, - MATCH_VWSMACCU_VX, - MATCH_VWSMACC_VX, - MATCH_VWSMACCSU_VX, - MATCH_VWSMACCUS_VX, + MATCH_VQMACCU_VX, + MATCH_VQMACC_VX, + MATCH_VQMACCSU_VX, + MATCH_VQMACCUS_VX, MATCH_VADD_VV, MATCH_VSUB_VV, MATCH_VMINU_VV, @@ -859,9 +859,9 @@ vectorUnit_t::vectorUnit_t() : MATCH_VWREDSUM_VS, MATCH_VDOTU_VV, MATCH_VDOT_VV, - MATCH_VWSMACCU_VV, - MATCH_VWSMACC_VV, - MATCH_VWSMACCSU_VV, + MATCH_VQMACCU_VV, + MATCH_VQMACC_VV, + MATCH_VQMACCSU_VV, MATCH_VADD_VI, MATCH_VRSUB_VI, MATCH_VAND_VI, diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index a1fc513..1e7764d 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -478,13 +478,6 @@ riscv_insn_ext_v_alu_int = \ vwmulu_vx \ vwredsum_vs \ vwredsumu_vs \ - vwsmacc_vv \ - vwsmacc_vx \ - vwsmaccsu_vv \ - vwsmaccsu_vx \ - vwsmaccu_vv \ - vwsmaccu_vx \ - vwsmaccus_vx \ vwsub_vv \ vwsub_vx \ vwsub_wv \ diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index a801b81..ddf40a4 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -922,10 +922,10 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV_S___INSN(vwredsum, 1); DISASM_OPIV_V___INSN(vdotu, 0); DISASM_OPIV_V___INSN(vdot, 1); - DISASM_OPIV_VX__INSN(vwsmaccu, 0); - DISASM_OPIV_VX__INSN(vwsmacc, 1); - DISASM_OPIV_VX__INSN(vwsmaccsu, 0); - DISASM_OPIV__X__INSN(vwsmaccus, 1); + DISASM_OPIV_VX__INSN(vqmaccu, 0); + DISASM_OPIV_VX__INSN(vqmacc, 1); + DISASM_OPIV__X__INSN(vqmaccus, 1); + DISASM_OPIV_VX__INSN(vqmaccsu, 0); //OPMVV/OPMVX //0b00_0000 @@ -991,8 +991,8 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV_VX__INSN(vwmul, 1); DISASM_OPIV_VX__INSN(vwmaccu, 0); DISASM_OPIV_VX__INSN(vwmacc, 1); - DISASM_OPIV_VX__INSN(vwmaccsu, 0); DISASM_OPIV__X__INSN(vwmaccus, 1); + DISASM_OPIV_VX__INSN(vwmaccsu, 0); #undef DISASM_OPIV_VXI_INSN #undef DISASM_OPIV_VX__INSN |