diff options
| -rw-r--r-- | riscv/decode.h | 20 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_x_f_w.h | 1 |
2 files changed, 18 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index e6e3cb7..c1fed9b 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -2185,6 +2185,20 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ DEBUG_RVV_FP_VV; \ VI_VFP_LOOP_END +#define VI_VFP_LOOP_SCALE_BASE \ + require_fp; \ + require_vector;\ + require((P.VU.vsew == e8 && p->supports_extension(EXT_ZFH)) || \ + (P.VU.vsew == e16 && p->supports_extension('F')) || \ + (P.VU.vsew == e32 && p->supports_extension('D'))); \ + reg_t vl = P.VU.vl; \ + reg_t rd_num = insn.rd(); \ + reg_t rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + softfloat_roundingMode = STATE.frm; \ + for (reg_t i=P.VU.vstart; i<vl; ++i){ \ + VI_LOOP_ELEMENT_SKIP(); + #define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, is_widen) \ if (is_widen) { \ VI_CHECK_DSS(false);\ @@ -2193,21 +2207,21 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ } \ switch(P.VU.vsew) { \ case e8: {\ - VI_VFP_LOOP_BASE \ + VI_VFP_LOOP_SCALE_BASE \ BODY8 \ set_fp_exceptions; \ VI_VFP_LOOP_END \ } \ break; \ case e16: {\ - VI_VFP_LOOP_BASE \ + VI_VFP_LOOP_SCALE_BASE \ BODY16 \ set_fp_exceptions; \ VI_VFP_LOOP_END \ } \ break; \ case e32: {\ - VI_VFP_LOOP_BASE \ + VI_VFP_LOOP_SCALE_BASE \ BODY32 \ set_fp_exceptions; \ VI_VFP_LOOP_END \ diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h index aed35e6..d816c59 100644 --- a/riscv/insns/vfncvt_x_f_w.h +++ b/riscv/insns/vfncvt_x_f_w.h @@ -3,6 +3,7 @@ VI_VFP_CVT_SCALE ({ auto vs2 = P.VU.elt<float16_t>(rs2_num, i); P.VU.elt<int8_t>(rd_num, i, true) = f16_to_i8(vs2, STATE.frm, true); + fprintf(stderr, "here 3 %ld %x %x\n", i, vs2.v, P.VU.elt<int8_t>(rd_num, i)); }, { auto vs2 = P.VU.elt<float32_t>(rs2_num, i); |