diff options
| -rw-r--r-- | riscv/decode.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfmv_f_s.h | 1 | ||||
| -rw-r--r-- | riscv/insns/vfmv_s_f.h | 1 |
3 files changed, 4 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index c64cacc..cdfee77 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1917,6 +1917,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ (P.VU.vsew == e32 && p->supports_extension('F')) || \ (P.VU.vsew == e64 && p->supports_extension('D'))); \ require_vector(true);\ + require(STATE.frm < 0x5);\ reg_t vl = P.VU.vl; \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ @@ -2303,6 +2304,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ require((P.VU.vsew == e8 && p->supports_extension(EXT_ZFH)) || \ (P.VU.vsew == e16 && p->supports_extension('F')) || \ (P.VU.vsew == e32 && p->supports_extension('D'))); \ + require(STATE.frm < 0x5);\ reg_t vl = P.VU.vl; \ reg_t rd_num = insn.rd(); \ reg_t rs1_num = insn.rs1(); \ diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h index 47e3c3b..4a81436 100644 --- a/riscv/insns/vfmv_f_s.h +++ b/riscv/insns/vfmv_f_s.h @@ -4,6 +4,7 @@ require_fp; require((P.VU.vsew == e16 && p->supports_extension(EXT_ZFH)) || (P.VU.vsew == e32 && p->supports_extension('F')) || (P.VU.vsew == e64 && p->supports_extension('D'))); +require(STATE.frm < 0x5); reg_t rs2_num = insn.rs2(); uint64_t vs2_0 = 0; diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index 4a4c105..52ed7b2 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -4,6 +4,7 @@ require_fp; require((P.VU.vsew == e16 && p->supports_extension(EXT_ZFH)) || (P.VU.vsew == e32 && p->supports_extension('F')) || (P.VU.vsew == e64 && p->supports_extension('D'))); +require(STATE.frm < 0x5); reg_t vl = P.VU.vl; |