diff options
| -rw-r--r-- | riscv/execute.cc | 2 | ||||
| -rw-r--r-- | riscv/mmu.h | 23 | ||||
| -rw-r--r-- | riscv/triggers.h | 13 |
3 files changed, 19 insertions, 19 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index ed03c0d..c57ca3d 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -309,7 +309,7 @@ void processor_t::step(size_t n) enter_debug_mode(DCSR_CAUSE_STEP); } } - catch (trigger_matched_t& t) + catch (triggers::matched_t& t) { if (mmu->matched_trigger) { // This exception came from the MMU. That means the instruction hasn't diff --git a/riscv/mmu.h b/riscv/mmu.h index b71f3c7..1ca2d9f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -38,19 +38,6 @@ struct tlb_entry_t { reg_t target_offset; }; -class trigger_matched_t -{ - public: - trigger_matched_t(int index, - triggers::operation_t operation, reg_t address, reg_t data) : - index(index), operation(operation), address(address), data(data) {} - - int index; - triggers::operation_t operation; - reg_t address; - reg_t data; -}; - // this class implements a processor's port into the virtual memory system. // an MMU and instruction cache are maintained for simulator performance. class mmu_t @@ -472,7 +459,7 @@ private: target_endian<uint16_t>* ptr = (target_endian<uint16_t>*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); int match = proc->TM.trigger_match(triggers::OPERATION_EXECUTE, addr, from_target(*ptr)); if (match >= 0) { - throw trigger_matched_t(match, triggers::OPERATION_EXECUTE, addr, from_target(*ptr)); + throw triggers::matched_t(match, triggers::OPERATION_EXECUTE, addr, from_target(*ptr)); } } return result; @@ -482,7 +469,7 @@ private: return (uint16_t*)(translate_insn_addr(addr).host_offset + addr); } - inline trigger_matched_t *trigger_exception(triggers::operation_t operation, + inline triggers::matched_t *trigger_exception(triggers::operation_t operation, reg_t address, reg_t data) { if (!proc) { @@ -492,9 +479,9 @@ private: if (match == -1) return NULL; if (proc->TM.triggers[match]->timing == 0) { - throw trigger_matched_t(match, operation, address, data); + throw triggers::matched_t(match, operation, address, data); } - return new trigger_matched_t(match, operation, address, data); + return new triggers::matched_t(match, operation, address, data); } reg_t pmp_homogeneous(reg_t addr, reg_t len); @@ -509,7 +496,7 @@ private: bool check_triggers_load; bool check_triggers_store; // The exception describing a matched trigger, or NULL. - trigger_matched_t *matched_trigger; + triggers::matched_t *matched_trigger; friend class processor_t; }; diff --git a/riscv/triggers.h b/riscv/triggers.h index 95c2dcc..dea4fdb 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -22,6 +22,19 @@ typedef enum ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT } action_t; +class matched_t +{ + public: + matched_t(int index, + triggers::operation_t operation, reg_t address, reg_t data) : + index(index), operation(operation), address(address), data(data) {} + + int index; + triggers::operation_t operation; + reg_t address; + reg_t data; +}; + class trigger_t { public: bool dmode; |