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-rw-r--r--riscv/processor.cc12
1 files changed, 0 insertions, 12 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index c109342..37e0d60 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -665,18 +665,6 @@ void processor_t::set_csr(int which, reg_t val)
case CSR_VXRM:
VU.vxrm = val;
break;
- case CSR_VL:
- VU.vl = val;
- break;
- case CSR_VTYPE:
- VU.vtype = val;
- // check vill bit
- if (BITS(VU.vtype, get_xlen(), get_xlen() - 1) == 1){
- VU.vill = true;
- }else{
- VU.vill = false;
- }
- break;
}
}