diff options
| -rw-r--r-- | riscv/decode.h | 2 | ||||
| -rw-r--r-- | riscv/mmu.cc | 3 | ||||
| -rw-r--r-- | riscv/trap.h | 4 |
3 files changed, 4 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 9890514..543080d 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -155,7 +155,7 @@ private: #define set_pc(x) \ do { if ((x) & 3 /* For now... */) \ - throw trap_instruction_address_misaligned(); \ + throw trap_instruction_address_misaligned(x); \ npc = sext_xprlen(x); \ } while(0) diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 4675f75..92cb6de 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -45,8 +45,7 @@ void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch) if(unlikely((pte_perm & perm) != perm)) { if (fetch) - throw trap_instruction_access_fault(); - + throw trap_instruction_access_fault(addr); if (store) throw trap_store_access_fault(addr); throw trap_load_access_fault(addr); diff --git a/riscv/trap.h b/riscv/trap.h index b795948..53df4f4 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -42,8 +42,8 @@ class mem_trap_t : public trap_t const char* name() { return "trap_"#x; } \ }; -DECLARE_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) -DECLARE_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault) +DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) +DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault) DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) DECLARE_TRAP(CAUSE_PRIVILEGED_INSTRUCTION, privileged_instruction) DECLARE_TRAP(CAUSE_FP_DISABLED, fp_disabled) |